公开(公告)号：US11030092B2

公开(公告)日：2021-06-08

申请号：US16748372

申请日：2020-01-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Xu ,  Qun Yu ,  Licheng Chen

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0866

Abstract: An access request processing apparatus comprises, a processor determines an object cache page according to a write request when receiving the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

公开(公告)号：US20200159655A1

公开(公告)日：2020-05-21

申请号：US16748372

申请日：2020-01-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Xu ,  Qun Yu ,  Licheng Chen

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0804

Abstract: An access request processing apparatus comprises, a processor determines an object cache page according to a write request when receiving the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

公开(公告)号：US09984003B2

公开(公告)日：2018-05-29

申请号：US15257506

申请日：2016-09-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Licheng Chen ,  Mingyu Chen

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/6042 ,  G06F2212/651 ,  G06F2212/653 ,  G06F2212/657

Abstract: A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

公开(公告)号：US20180300236A1

公开(公告)日：2018-10-18

申请号：US16018602

申请日：2018-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Xu ,  Qun Yu ,  Licheng Chen

IPC: G06F12/02 ,  G06F3/06

Abstract: An access request processing method and apparatus, and a computer system is disclosed. The computer system includes a processor and a non-volatile memory (NVM). When receiving a write request, the processor determines an object cache page according to the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

公开(公告)号：US09870327B2

公开(公告)日：2018-01-16

申请号：US14335029

申请日：2014-07-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4239

Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

公开(公告)号：US09846626B2

公开(公告)日：2017-12-19

申请号：US14754011

申请日：2015-06-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Mingyu Chen ,  Licheng Chen ,  Mingyang Chen

IPC: G06F13/00 ,  G06F11/30 ,  G06F13/16 ,  G06F12/10 ,  G06F11/34 ,  G06F12/12

CPC classification number: G06F11/3037 ,  G06F11/3027 ,  G06F11/3452 ,  G06F11/3466 ,  G06F12/10 ,  G06F12/12 ,  G06F13/1663 ,  G06F2201/815 ,  G06F2201/88

Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

公开(公告)号：US20150212944A1

公开(公告)日：2015-07-30

申请号：US14680262

申请日：2015-04-07

Applicant: Huawei Technologies Co. Ltd.

Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0866 ,  G06F17/30132 ,  G06F2212/1024 ,  G06F2212/312 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.

Abstract translation: 公开了一种用于将存储器数据从存储器推送到用于存储由计算系统中的中央处理单元（CPU）预取的数据的推送目的地存储器的方法和装置。 在该方法中，计算系统的存储器控​​制器根据推送周期周期性地产生推送命令。 然后，存储器控制器根据推送命令获取待推送数据的推送参数，并根据推送参数向存储器发送至少一个存储器访问请求，其中至少一个存储器访问请求被用于请求 从存储器中推送数据。 存储器控制器在接收到根据存储器的至少一个存储器访问请求发送的被推送数据之后，缓冲被推送的数据并将待推送的数据从数据缓冲器推送到 推送目的地存储。

公开(公告)号：US09632938B2

公开(公告)日：2017-04-25

申请号：US14680262

申请日：2015-04-07

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen

IPC: G06F12/08 ,  G06F12/0862 ,  G06F17/30 ,  G06F12/0866

CPC classification number: G06F12/0862 ,  G06F12/0866 ,  G06F17/30132 ,  G06F2212/1024 ,  G06F2212/312 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.

公开(公告)号：US20170075818A1

公开(公告)日：2017-03-16

申请号：US15343693

申请日：2016-11-04

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F3/06

CPC classification number: G06F12/1027 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0664 ,  G06F3/0685 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/684

Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

Abstract translation: 一种存储器管理方法和装置，其中所述方法包括：接收存储器访问请求，其中所述存储器访问请求携带虚拟地址; 如果在翻译后备缓冲器TLB和存储器中找到与虚拟地址相对应的页表条目，则确定虚拟地址的页面错误类型; 如果虚拟地址的页面错误类型是由空白页引起的页面错误，其中由空白页引起的页面错误意味着没有对应的页面被分配给虚拟地址，则将对应的页面分配给虚拟地址; 以及将与虚拟地址相对应的页表条目更新到存储器和TLB。 当出现空白页引起的页面错误时，内存管理器不会生成页面错误，但会将相应的页面分配给虚拟地址。 因此，页面错误的发生量减少，从而提高存储器管理效率。

公开(公告)号：US20150293859A1

公开(公告)日：2015-10-15

申请号：US14751368

申请日：2015-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan ,  Licheng Chen

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present invention are mainly used in a process of processing a memory access request.

Abstract translation: 存储器访问处理方法基于与电子设备领域相关的存储器芯片互连，存储器芯片和系统，并且可以缩短处理存储器访问请求的时间延迟并提高系统带宽的利用率。 本发明的方法包括：由第一存储器芯片接收存储器访问请求; 并且如果第一存储器芯片不是与存储器访问请求对应的目标存储器芯片，则根据预配置的路由规则将存储器访问请求发送到与第一存储器芯片连接的下一个存储器芯片，直到目标存储器芯片对应 到存储器访问请求被确定。 本发明的实施例主要用于处理存储器访问请求的过程。