知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.018 seconds)

    Memory management and device
    1.
    发明授权
    Memory management and device 有权

    公开(公告)号：US10552337B2

    公开(公告)日：2020-02-04

    申请号：US15343693

    申请日：2016-11-04

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

    Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

    IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/1009

    Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

    DRAM refresh method, apparatus, and system
    3.
    发明授权
    DRAM refresh method, apparatus, and system 有权

    公开(公告)号：US10586608B2

    公开(公告)日：2020-03-10

    申请号：US15802781

    申请日：2017-11-03

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Shihai Xiao ,  Yongbing Huang ,  Rui He

    IPC: G11C11/40 ,  G11C29/00 ,  G11C11/406 ,  G11C11/4091

    Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

    REFRESH CONTROL METHOD AND APPARATUS OF DISPLAY DEVICE
    5.
    发明申请
    REFRESH CONTROL METHOD AND APPARATUS OF DISPLAY DEVICE 审中-公开

    公开(公告)号：US20170148422A1

    公开(公告)日：2017-05-25

    申请号：US15426356

    申请日：2017-02-07

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

    Inventor： Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Shihai Xiao

    IPC: G09G5/395 ,  G09G5/00

    CPC classification number: G09G5/395 ,  G09G3/3611 ,  G09G3/3688 ,  G09G5/399 ,  G09G2310/04 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/18

    Abstract: A refresh control method and apparatus of a display device are disclosed, where the method includes: (201) periodically generating, a first refresh signal, and outputting an image frame for display that is stored in a frame buffer to a display panel; and (202) generating, a second refresh signal when determining that the image frame for display that is stored in the frame buffer changes, and outputting the image frame for display that is stored in the frame buffer to the display panel. A generation frequency of the second refresh signal is far less than a frequency required to ensure timely display of an image frame. In addition, an operation of refreshing an image frame is triggered by using an event, which may ensure timely display of the image frame, and avoid an unnecessary refresh operation, so as to reduce system resource consumption and memory consumption.

    MEMORY MANAGEMENT METHOD AND DEVICE
    6.
    发明申请
    MEMORY MANAGEMENT METHOD AND DEVICE 审中-公开
    内存管理方法和设备

    公开(公告)号：US20170075818A1

    公开(公告)日：2017-03-16

    申请号：US15343693

    申请日：2016-11-04

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

    Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

    IPC: G06F12/1027 ,  G06F12/1009 ,  G06F3/06

    CPC classification number: G06F12/1027 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0664 ,  G06F3/0685 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/684

    Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

    Abstract translation: 一种存储器管理方法和装置，其中所述方法包括：接收存储器访问请求，其中所述存储器访问请求携带虚拟地址; 如果在翻译后备缓冲器TLB和存储器中找到与虚拟地址相对应的页表条目，则确定虚拟地址的页面错误类型; 如果虚拟地址的页面错误类型是由空白页引起的页面错误，其中由空白页引起的页面错误意味着没有对应的页面被分配给虚拟地址，则将对应的页面分配给虚拟地址; 以及将与虚拟地址相对应的页表条目更新到存储器和TLB。 当出现空白页引起的页面错误时，内存管理器不会生成页面错误，但会将相应的页面分配给虚拟地址。 因此，页面错误的发生量减少，从而提高存储器管理效率。

    Memory Access Processing Method, Memory Chip, and System Based on Memory Chip Interconnection
    7.
    发明申请
    Memory Access Processing Method, Memory Chip, and System Based on Memory Chip Interconnection 有权
    存储器存取处理方法，存储芯片和基于存储芯片互连的系统

    公开(公告)号：US20150293859A1

    公开(公告)日：2015-10-15

    申请号：US14751368

    申请日：2015-06-26

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan ,  Licheng Chen

    IPC: G06F12/14 ,  G06F3/06

    CPC classification number: G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

    Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present invention are mainly used in a process of processing a memory access request.

    Abstract translation: 存储器访问处理方法基于与电子设备领域相关的存储器芯片互连，存储器芯片和系统，并且可以缩短处理存储器访问请求的时间延迟并提高系统带宽的利用率。 本发明的方法包括：由第一存储器芯片接收存储器访问请求; 并且如果第一存储器芯片不是与存储器访问请求对应的目标存储器芯片，则根据预配置的路由规则将存储器访问请求发送到与第一存储器芯片连接的下一个存储器芯片，直到目标存储器芯片对应 到存储器访问请求被确定。 本发明的实施例主要用于处理存储器访问请求的过程。

    MESSAGE-BASED MEMORY ACCESS APPARATUS AND ACCESS METHOD THEREOF
    8.
    发明申请
    MESSAGE-BASED MEMORY ACCESS APPARATUS AND ACCESS METHOD THEREOF 有权
    基于消息的存储器访问设备及其访问方法

    公开(公告)号：US20150006841A1

    公开(公告)日：2015-01-01

    申请号：US14335029

    申请日：2014-07-18

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

    IPC: G06F13/16

    CPC classification number: G06F13/1673 ,  G06F13/4239

    Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

    Abstract translation: 公开了一种基于消息的存储器访问装置及其访问方法，基于消息的存储器访问装置包括：基于消息的命令总线，被配置为发送由CPU生成的基于消息的存储器访问指令，以指示存储器系统 执行相应的操作; 基于消息的存储器控​​制器，被配置为将CPU请求打包到消息分组中并将所述分组发送到存储模块，并且解析由所述存储模块返回的消息分组并将数据返回到所述CPU; 消息信道，被配置为发送请求消息分组和响应消息分组; 以及所述存储模块，包括缓冲器调度器，并且被配置为从所述基于消息的存储器控​​制器接收所述请求分组并处理相应的请求。

    CACHE MANAGEMENT METHOD, CACHE CONTROLLER, AND COMPUTER SYSTEM
    9.
    发明申请
    CACHE MANAGEMENT METHOD, CACHE CONTROLLER, AND COMPUTER SYSTEM 审中-公开

    公开(公告)号：US20180314646A1

    公开(公告)日：2018-11-01

    申请号：US16028265

    申请日：2018-07-05

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Jun Xu ,  Yongbing Huang ,  Yuangang Wang

    IPC: G06F12/121 ,  G06F12/0871 ,  G06F12/0804

    CPC classification number: G06F12/121 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0871 ,  G06F12/122 ,  G06F2212/1021

    Abstract: A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.

Patent Agency Ranking