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    Memory access method, buffer scheduler and memory module
    1.
    发明授权
    Memory access method, buffer scheduler and memory module 有权

    公开(公告)号：US09785551B2

    公开(公告)日：2017-10-10

    申请号：US14953320

    申请日：2015-11-28

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

    Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

    Mapping Processing Method and Apparatus for Cache Address
    2.
    发明申请
    Mapping Processing Method and Apparatus for Cache Address 有权
    缓存地址的映射处理方法和装置

    公开(公告)号：US20160371198A1

    公开(公告)日：2016-12-22

    申请号：US15257506

    申请日：2016-09-06

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zehan Cui ,  Licheng Chen ,  Mingyu Chen

    IPC: G06F12/1027 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0842

    CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/6042 ,  G06F2212/651 ,  G06F2212/653 ,  G06F2212/657

    Abstract: A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

    Abstract translation: 一种用于高速缓存地址的映射处理方法和装置，其中该方法包括获取对应于由处理核心发送的访问地址的物理地址，其中物理地址包括物理页号（PPN）和页偏移量， 地址到缓存地址，其中缓存地址包括缓存集索引1，缓存标签，高速缓存集索引2和高速缓存块偏移顺序，其中高速缓存集索引1具有高位位，高速缓存 将低位位置索引2一起形成缓存集索引，缓存集索引1落在PPN的范围内。 巨大页面PPN的PPN的一些位被映射到Cache的设置索引，使得可以由操作系统对这些位进行着色。

    Memory Access Method, Buffer Scheduler and Memory Module
    3.
    发明申请
    Memory Access Method, Buffer Scheduler and Memory Module 有权
    内存访问方法，缓冲区调度程序和内存模块

    公开(公告)号：US20160085670A1

    公开(公告)日：2016-03-24

    申请号：US14953320

    申请日：2015-11-28

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

    Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

    Abstract translation: 本发明公开了一种存储器访问方法，缓冲器调度器和存储器模块，其可以在不改变存储器模块或存储器芯片的情况下支持多种应用场景。 该方法包括：接收用于存储器访问数据的操作请求消息，其中操作请求消息包括存储器访问数据的标签信息，存储器访问数据的操作信息和存储器访问数据的存储器地址; 并且根据存储器访问数据的标签信息，存储器访问数据的存储器地址和存储器访问数据的操作信息中的至少一个来执行对存储器访问数据的标签的操作和/或 存储器存储数据存储在存储器模块中。 本发明可应用于计算机领域。

    Method for accessing extended memory, device, and system
    4.
    发明授权
    Method for accessing extended memory, device, and system 有权

    公开(公告)号：US11237728B2

    公开(公告)日：2022-02-01

    申请号：US16744795

    申请日：2020-01-16

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

    IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/02

    Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

    Address Compression Method, Address Decompression Method, Compressor, and Decompressor
    6.
    发明申请
    Address Compression Method, Address Decompression Method, Compressor, and Decompressor 有权
    地址压缩方法，地址解压缩方法，压缩器和解压缩器

    公开(公告)号：US20150220448A1

    公开(公告)日：2015-08-06

    申请号：US14687607

    申请日：2015-04-15

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Yuan Ruan

    IPC: G06F12/10 ,  G06F9/30 ,  G06F9/35

    CPC classification number: H03M7/6011 ,  G06F9/30138 ,  G06F9/35 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/385 ,  G06F17/30153 ,  G06F2212/6032 ,  G06F2212/657

    Abstract: An address compression method, an address decompression method, a compressor, and a decompressor, which can improve an address compression ratio. The address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.

    Abstract translation: 地址压缩方法，地址解压缩方法，压缩器和解压缩器，可以提高地址压缩比。 地址压缩方法包括在压缩机接收到由第一处理器发送的多个操作请求消息之后，根据由具有相同流号的所有操作请求消息中携带的地址信息形成的地址特征，确定与 具有相同流号码的操作请求消息; 然后根据确定的压缩算法压缩具有相同流号的操作请求消息中承载的地址。 本发明可应用于计算机领域。

    Memory management and device
    7.
    发明授权
    Memory management and device 有权

    公开(公告)号：US10552337B2

    公开(公告)日：2020-02-04

    申请号：US15343693

    申请日：2016-11-04

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

    Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

    IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/1009

    Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

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