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    Digital signal processor with addressable and shifting memory
    1.
    发明授权
    Digital signal processor with addressable and shifting memory 失效
    具有可寻址和移位存储器的数字信号处理器

    公开(公告)号：US4811267A

    公开(公告)日：1989-03-07

    申请号：US162306

    申请日：1988-02-29

    Applicant: Hideki Ando ,  Harufusa Kondo ,  Hirohisa Machida

    Inventor： Hideki Ando ,  Harufusa Kondo ,  Hirohisa Machida

    IPC: G06F17/10 ,  G06F7/544 ,  G06F17/16 ,  G06F7/38

    CPC classification number: G06F7/5443

    Abstract: A digital signal processor includes a digital memory, a controller, an arithmetic operation unit and an interconnecting bus. The memory includes a shift register having an addressable output for storing values which are supplied to a multiplier circuit of the arithmetic operation unit. Use of the shift register provides a data delay minimizing the number of instructions required to implement delay processing. In the arithmetic operation unit, the output from the multiplier is connected to an arithmetic logic unit which, in turn, is connected to an accumulator. The accumulator temporarily stores data from the arithmetic logic unit and output the result onto the data bus. The operations of the signal process are directed by the controller which includes a program memory, an instruction register, and an instruction decoder.

    Abstract translation: 数字信号处理器包括数字存储器，控制器，算术运算单元和互连总线。 存储器包括具有可寻址输出的移位寄存器，用于存储提供给算术运算单元的乘法器电路的值。 使用移位寄存器提供数据延迟，最小化实现延迟处理所需的指令数量。 在算术运算单元中，乘法器的输出连接到算术逻辑单元，算术逻辑单元又连接到累加器。 累加器临时存储来自算术逻辑单元的数据，并将结果输出到数据总线上。 信号处理的操作由包括程序存储器，指令寄存器和指令译码器的控制器引导。

    Address translator having a high speed data comparator
    3.
    发明授权
    Address translator having a high speed data comparator 失效
    具有高速数据比较器的地址转换器

    公开(公告)号：US5386528A

    公开(公告)日：1995-01-31

    申请号：US874921

    申请日：1992-04-29

    Applicant: Hideki Ando ,  Hirohisa Machida

    Inventor： Hideki Ando ,  Hirohisa Machida

    IPC: G06F7/02 ,  G06F12/10 ,  G06F12/12 ,  G11C15/00

    CPC classification number: G11C15/00 ,  G06F12/123 ,  G06F7/02 ,  G06F12/1027

    Abstract: An address translator has an improved data comparison circuit for comparing two pieces of data having n bits, e.g., 12 bits. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. Hence, delay of signal propagation which may occur in the cell circuit in which the match is detected is reduced.

    Abstract translation: 地址转换器具有改进的数据比较电路，用于比较具有n位的两个数据，例如12位。 在数据比较电路中，单元电路对每个相应的4位数据进行比较。 当在一组4比特的比较中检测到匹配时，旁路表示低位比特的比较结果的信号。 因此，可以在检测到匹配的单元电路中发生的信号传播的延迟减小。

    Arithmetic and logic unit with prior state dependent logic operations
    4.
    发明授权
    Arithmetic and logic unit with prior state dependent logic operations 失效
    具有先前状态相关逻辑运算的算术逻辑单元

    公开(公告)号：US4821225A

    公开(公告)日：1989-04-11

    申请号：US042532

    申请日：1987-04-27

    Applicant: Hideki Ando ,  Hirohisa Machida

    Inventor： Hideki Ando ,  Hirohisa Machida

    IPC: G06F7/00 ,  G06F7/575 ,  G06F7/38

    CPC classification number: G06F7/575

    Abstract: The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps.The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.

    Abstract translation: 本发明是具有改进的硬件的微处理器的算术和逻辑单元，以通过少量指令步骤执行诸如MAD（修改加法）的操作的指定操作。 本发明的算术和逻辑单元具有控制部分，该控制部分设置有用于通过少量指令步骤执行诸如MAD的操作的指定操作的控制电路。

    Register window system for reducing the need for overflow-write by prewriting registers to memory during times without bus contention
    5.
    发明授权
    Register window system for reducing the need for overflow-write by prewriting registers to memory during times without bus contention 失效
    寄存器窗口系统，用于在没有总线争用的时间内通过预写寄存器到存储器来减少溢出写入的需要

    公开(公告)号：US5233691A

    公开(公告)日：1993-08-03

    申请号：US450633

    申请日：1989-12-13

    Applicant: Hideki Ando ,  Hirohisa Machida

    Inventor： Hideki Ando ,  Hirohisa Machida

    IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40

    CPC classification number: G06F9/30127 ,  G06F9/4425

    Abstract: A reduced instruction set computer which adopts a configuration of controlling in a manner that in response to an access to a register file, the using state of an external bus or the like, if possible, in a period before an overflow of the register file takes place, register windows used in the procedure called in the past are made to save in advance into a stack of a memory, as a result, there is a high possibility that processing of making the register windows save into the stack of the memory has been already completed even if an overflow takes place in the register file, whereby being capable of dispensing with saving processing of the register window into the stack at this point.

    Abstract translation: 一种简化指令集计算机，其以在寄存器文件的溢出之前的一段时间内以可能的方式响应于访问寄存器文件，外部总线的使用状态等的方式进行控制的配置 过去调用的过程中使用的寄存器窗口被预先保存到存储器的堆栈中，结果是存储器的堆栈中的寄存器窗口的处理被存储的可能性很高 即使在寄存器文件中发生溢出也已经完成，从而能够在此时将登记窗口的保存处理分配到堆栈中。

    SCREENING METHOD UTILIZING THALIDOMIDE-TARGETING FACTOR
    7.
    发明申请
    SCREENING METHOD UTILIZING THALIDOMIDE-TARGETING FACTOR 有权
    筛选方法利用半胱氨酸靶向因子

    公开(公告)号：US20120192297A1

    公开(公告)日：2012-07-26

    申请号：US13498067

    申请日：2010-10-18

    Applicant: Hiroshi Handa ,  Hideki Ando ,  Takumi Itoh ,  Kentaro Hotta

    Inventor： Hiroshi Handa ,  Hideki Ando ,  Takumi Itoh ,  Kentaro Hotta

    IPC: G01N33/68 ,  C12N15/12 ,  A01K67/027 ,  C07K14/435

    CPC classification number: G01N33/566 ,  G01N2500/04

    Abstract: With an aim to provide means for developing a compound devoid of teratogenicity but retaining beneficial actions, a screening method for a non-teratogenic substance comprising bringing a test substance into contact with cereblon or a fragment of cereblon, evaluating the bindability of the test substance with cereblon or the fragment of cereblon, and selecting a test substance that does not bind to cereblon or the fragment of cereblon or a test substance exhibiting lower bindability with cereblon or the fragment of cereblon than does thalidomide is provided.

    Abstract translation: 目的是提供开发不具有致畸性但保留有益作用的化合物的方法，用于非致畸物质的筛选方法，包括使测试物质与大脑或脑片的片段接触，评估测试物质与 提供了与沙门氏菌相比，不能结合到脑部或与本发明的化合物相比较的表现出与巧克力片或巧克力片相比具有较低粘合性的测试物质的测试物质。

    Clustered superscalar processor and communication control method between clusters in clustered superscalar processor
    10.
    发明申请
    Clustered superscalar processor and communication control method between clusters in clustered superscalar processor 失效
    集群超标量处理器中的集群超标量处理器和集群之间的通信控制方法

    公开(公告)号：US20060095736A1

    公开(公告)日：2006-05-04

    申请号：US11071794

    申请日：2005-03-03

    Applicant: Hideki Ando ,  Hajime Shimada ,  Atsushi Mochizuki

    Inventor： Hideki Ando ,  Hajime Shimada ,  Atsushi Mochizuki

    IPC: G06F9/30

    CPC classification number: G06F9/3885 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/3891

    Abstract: A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the instruction that will be stored in the instruction window and a previous instruction stored in the instruction window. When there is a data dependency relationship, the execution result of the previous instruction of one cluster is communicated to a register cache of another cluster that executes the instruction having a data dependency relationship with the previous instruction.

    Abstract translation: 集群超标量处理器，用于减少寄存器缓存的未命中率，并减少错误处罚的可能性。 在指令窗口中存储指令之前，处理器检查是否存在将存储在指令窗口中的指令与存储在指令窗口中的先前指令之间的数据依赖关系。 当存在数据依赖关系时，一个簇的先前指令的执行结果被传送到执行与先前指令具有数据依赖关系的指令的另一个簇的寄存器高速缓存。

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