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公开(公告)号：US4811267A
公开(公告)日：1989-03-07
申请号：US162306
申请日：1988-02-29
Applicant: Hideki Ando , Harufusa Kondo , Hirohisa Machida
Inventor： Hideki Ando , Harufusa Kondo , Hirohisa Machida
CPC classification number: G06F7/5443
Abstract: A digital signal processor includes a digital memory, a controller, an arithmetic operation unit and an interconnecting bus. The memory includes a shift register having an addressable output for storing values which are supplied to a multiplier circuit of the arithmetic operation unit. Use of the shift register provides a data delay minimizing the number of instructions required to implement delay processing. In the arithmetic operation unit, the output from the multiplier is connected to an arithmetic logic unit which, in turn, is connected to an accumulator. The accumulator temporarily stores data from the arithmetic logic unit and output the result onto the data bus. The operations of the signal process are directed by the controller which includes a program memory, an instruction register, and an instruction decoder.
Abstract translation: 数字信号处理器包括数字存储器，控制器，算术运算单元和互连总线。 存储器包括具有可寻址输出的移位寄存器，用于存储提供给算术运算单元的乘法器电路的值。 使用移位寄存器提供数据延迟，最小化实现延迟处理所需的指令数量。 在算术运算单元中，乘法器的输出连接到算术逻辑单元，算术逻辑单元又连接到累加器。 累加器临时存储来自算术逻辑单元的数据，并将结果输出到数据总线上。 信号处理的操作由包括程序存储器，指令寄存器和指令译码器的控制器引导。
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公开(公告)号：US4771379A
公开(公告)日：1988-09-13
申请号：US922031
申请日：1986-10-21
Applicant: Hideki Ando , Masao Nakaya , Harufusa Kondo
Inventor： Hideki Ando , Masao Nakaya , Harufusa Kondo
CPC classification number: G06F9/3001 , G06F7/5443 , G06F9/3885
Abstract: An arithmetic operation portion 3 comprises a plurality of multipliers 311 and 312 connected directly with a memory portion 1 so that multiplication processing can be performed in parallel. As a result, the processing capacity for multiplication and addition can be increased and the throughput rate of data can be improved.
Abstract translation: 算术运算部3包括与存储部1直接连接的多个乘法器311,312，能够并行地进行乘法处理。 结果，可以增加乘法和加法的处理能力，并且可以提高数据的吞吐率。
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公开(公告)号：US20100150567A1
公开(公告)日：2010-06-17
申请号：US12423931
申请日：2009-04-15
Applicant: Harufusa Kondo , Masahiko Ishiwaki
Inventor： Harufusa Kondo , Masahiko Ishiwaki
IPC: H04B10/00
CPC classification number: H04B10/40
Abstract: An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination dates when the optical transceiver terminates the optical transmitting and receiving operation.
Abstract translation: 光收发器执行光发送和接收操作，并且具有第一存储器和外部接口。 外部接口从主机设备接收信息，并将接收的信息写入第一存储器。 外部接口响应于外部命令从第一个存储器读取信息，并从外部读取读取的信息。 该信息包括当光收发器开始光发送和接收操作时的操作开始日期和光收发器终止光发送和接收操作时的操作终止日期。
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公开(公告)号：US08184985B2
公开(公告)日：2012-05-22
申请号：US12205945
申请日：2008-09-08
Applicant: Harufusa Kondo , Tetsuhiro Fukao , Mutsumi Nakamaru
Inventor： Harufusa Kondo , Tetsuhiro Fukao , Mutsumi Nakamaru
IPC: H04B10/00
Abstract: A control circuit for an optical transmitter/receiver that transmits/receives an optical signal, comprises: a memory having a digital value storage area and an area that stores limit values; a register; an analog/digital conversion circuit that receives analog signals indicating operating parameters of the optical transmitter/receiver, converts the analog signals to respective digital values, and stores the digital values in the memory; a comparison logical circuit that compares the digital values with the limit values, generates flag values, and stores the flag values in the register; and an outside interface that allows an outside host apparatus to access the memory and the register to read the flag values and monitor an operating condition of the optical transmitter/receiver from outside.
Abstract translation: 一种用于发送/接收光信号的光发射机/接收机的控制电路，包括：具有数字值存储区域和存储极限值的区域的存储器; 登记册 模拟/数字转换电路，其接收指示光发送器/接收器的操作参数的模拟信号，将模拟信号转换为相应的数字值，并将数字值存储在存储器中; 将数字值与极限值进行比较的比较逻辑电路，生成标志值，并将标志值存储在寄存器中; 以及允许外部主机装置访问存储器和寄存器以读取标志值并从外部监视光发送器/接收器的操作条件的外部接口。
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公开(公告)号：US20100150578A1
公开(公告)日：2010-06-17
申请号：US12464174
申请日：2009-05-12
Applicant: Tetsuhiro Fukao , Harufusa Kondo , Kenichi Uto
Inventor： Tetsuhiro Fukao , Harufusa Kondo , Kenichi Uto
IPC: H04B10/04
CPC classification number: H04B10/572
Abstract: An optical transceiver includes an optical transmitter. The optical transmitter varies the wavelength of its output beam in accordance with the setting of a digital to analog converter. Two split beams emerging respectively from beam splitters are introduced into a photodetector and a wavelength filter, respectively. A quotient is calculated by dividing the digital value output from an analog to digital converter (ADC) by the digital value output from another ADC. A memory address m is then determined based on this quotient without making any calculation for compensating for the imperfect characteristics of the wavelength filter. A wavelength notification value is then selected from a wavelength notification table based on the determined memory address m, and sent to the system host.
Abstract translation: 光收发器包括光发射机。 光发射机根据数模转换器的设置来改变其输出光束的波长。 分别从分束器出射的两个分离光束分别被引入到光电检测器和波长滤波器中。 通过将来自模数转换器（ADC）的数字值输出除以另一ADC的数字值输出来计算商。 然后基于该商确定存储器地址m，而不进行用于补偿波长滤波器的不完美特性的任何计算。 然后根据确定的存储器地址m从波长通知表中选择波长通知值，并发送给系统主机。
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Patent Agency Ranking
公开(公告)号：US06873209B2
公开(公告)日：2005-03-29
申请号：US10670217
申请日：2003-09-26
Applicant: Kengo Takata , Tsutomu Yoshimura , Harufusa Kondo , Hironobu Ito
Inventor： Kengo Takata , Tsutomu Yoshimura , Harufusa Kondo , Hironobu Ito
IPC: H03K19/0175 , H03F3/45 , H04L25/02
CPC classification number: H03F3/45748 , H03F2203/45342 , H03F2203/45652
Abstract: An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.
Abstract translation: 获得了没有电路性能下降的输入缓冲器电路和与前一级电路的连接类型的限制。 输出信号（OUTB）输入到第一低通滤波器电路，第一低通滤波器电路对输出信号（OUTB）进行积分。 积分的结果作为电压值（V2a）存储在电容器（4s）中。 以相同的方式，将输出信号（OUT）输入到第二低通滤波器电路，并且第二低通滤波器电路对输出信号（OUT）进行积分。 积分的结果作为电压值（V2b）存储在电容器（4t）中。 差分放大器电路（5）通过放大电压值（V2a和V2b），根据晶体管（1x和1y）的设计规格产生适当的电压（V3a和V3b）并将其输出。 电压（V3a和V3b）分别施加在晶体管（1x和1y）的相应后栅上。
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公开(公告)号：US5053642A
公开(公告)日：1991-10-01
申请号：US508724
申请日：1990-04-13
Applicant: Kazuya Ishihara , Hiroshi Segawa , Chikako Ikenaga , Yoshitsugu Inoue , Atsushi Kurimoto , Harufusa Kondo , Takeo Nakabayashi
Inventor： Kazuya Ishihara , Hiroshi Segawa , Chikako Ikenaga , Yoshitsugu Inoue , Atsushi Kurimoto , Harufusa Kondo , Takeo Nakabayashi
CPC classification number: G06F13/4077 , Y02B60/1228 , Y02B60/1235
Abstract: A bus circuit comprises a bus interconnection (1) and a plurality of local bus interconnections (10). A plurality of circuit blocks (21a to 21d) are connected to each of the plurality of local bus interconnections (10). A multiplexer (70), a bus driver (60) and a transmitting circuit (80A) are provided corresponding to each of the local bus interconnections (10). Each multiplexer (70) selects one of the outputs from the corresponding plurality of circuit blocks (21a to 21d) and applies the selected one to the bus driver (60). The bus driver (60) drives the bus interconnection (1) according to the output of the multiplexer (70). The local bus interconnections (10) are precharged to a predetermined potential in advance. When any of the plurality of transmitting circuits (80A) is selected, the selected transmitting circuit (80A) either discharges the corresponding local bus interconnection (10) or holds the same at a predetermined potential according to the information on the bus interconnection (1).
Abstract translation: 总线电路包括总线互连（1）和多个局部总线互连（10）。 多个电路块（21a至21d）连接到多个局部总线互连（10）中的每一个。 对应于每个局部总线互连（10），提供多路复用器（70），总线驱动器（60）和发送电路（80A）。 每个多路复用器（70）从对应的多个电路块（21a至21d）中选择一个输出，并将所选择的一个施加到总线驱动器（60）。 总线驱动器（60）根据多路复用器（70）的输出驱动总线互连（1）。 预先将本地总线互连（10）预充电到预定电位。 当选择多个发送电路（80A）中的任何一个时，所选择的发送电路（80A）根据总线互连（1）上的信息，放电相应的局部总线互连（10）或将其保持在预定电位， 。
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公开(公告)号：US08385750B2
公开(公告)日：2013-02-26
申请号：US12464174
申请日：2009-05-12
Applicant: Tetsuhiro Fukao , Harufusa Kondo , Kenichi Uto
Inventor： Tetsuhiro Fukao , Harufusa Kondo , Kenichi Uto
IPC: H04B10/04
CPC classification number: H04B10/572
Abstract: An optical transceiver includes an optical transmitter. The optical transmitter varies the wavelength of its output beam in accordance with the setting of a digital to analog converter. Two split beams emerging respectively from beam splitters are introduced into a photodetector and a wavelength filter, respectively. A quotient is calculated by dividing the digital value output from an analog to digital converter (ADC) by the digital value output from another ADC. A memory address m is then determined based on this quotient without making any calculation for compensating for the imperfect characteristics of the wavelength filter. A wavelength notification value is then selected from a wavelength notification table based on the determined memory address m, and sent to the system host.
Abstract translation: 光收发器包括光发射机。 光发射机根据数模转换器的设置来改变其输出光束的波长。 分别从分束器出射的两个分离光束分别被引入到光电检测器和波长滤波器中。 通过将来自模数转换器（ADC）的数字值输出除以另一ADC的数字值输出来计算商。 然后基于该商确定存储器地址m，而不进行用于补偿波长滤波器的不完美特性的任何计算。 然后根据确定的存储器地址m从波长通知表中选择波长通知值，并发送给系统主机。
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公开(公告)号：US07912375B2
公开(公告)日：2011-03-22
申请号：US12423931
申请日：2009-04-15
Applicant: Harufusa Kondo , Masahiko Ishiwaki
Inventor： Harufusa Kondo , Masahiko Ishiwaki
IPC: H04B10/00
CPC classification number: H04B10/40
Abstract: An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination date, when the optical transceiver terminates the optical transmitting and receiving operation.
Abstract translation: 光收发器执行光发送和接收操作，并且具有第一存储器和外部接口。 外部接口从主机设备接收信息，并将接收的信息写入第一存储器。 外部接口响应于外部命令从第一个存储器读取信息，并从外部读取读取的信息。 当光收发器终止光发送和接收操作时，该信息包括当光收发器开始光发送和接收操作时的操作开始日期和操作终止日期中的至少一个。
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公开(公告)号：US20090279885A1
公开(公告)日：2009-11-12
申请号：US12205945
申请日：2008-09-08
Applicant: Harufusa Kondo , Tetsuhiro Fukao , Mutsumi Nakamaru
Inventor： Harufusa Kondo , Tetsuhiro Fukao , Mutsumi Nakamaru
IPC: H04B17/00
Abstract: A control circuit for an optical transmitter/receiver that transmits/receives an optical signal, comprises: a memory having a digital value storage area and an area that stores limit values; a register; an analog/digital conversion circuit that receives analog signals indicating operating parameters of the optical transmitter/receiver, converts the analog signals to respective digital values, and stores the digital values in the memory; a comparison logical circuit that compares the digital values with the limit values, generates flag values, and stores the flag values in the register; and an outside interface that allows an outside host apparatus to access the memory and the register to read the flag values and monitor an operating condition of the optical transmitter/receiver from outside.
Abstract translation: 一种用于发送/接收光信号的光发射机/接收机的控制电路，包括：具有数字值存储区域和存储极限值的区域的存储器; 登记册 模拟/数字转换电路，其接收指示光发送器/接收器的操作参数的模拟信号，将模拟信号转换为相应的数字值，并将数字值存储在存储器中; 将数字值与极限值进行比较的比较逻辑电路，生成标志值，并将标志值存储在寄存器中; 以及允许外部主机装置访问存储器和寄存器以读取标志值并从外部监视光发送器/接收器的操作条件的外部接口。
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