公开(公告)号：US5943379A

公开(公告)日：1999-08-24

申请号：US873118

申请日：1997-06-11

Applicant: Hee Wong ,  Gabriel Ming-Yu Li

Inventor： Hee Wong ,  Gabriel Ming-Yu Li

IPC: H03L7/08 ,  H03L7/089 ,  H03L7/099 ,  H03D3/24 ,  H04L7/00 ,  H04L25/36 ,  H04L25/40

CPC classification number: H03L7/0995 ,  H03L7/08 ,  H03L7/089

Abstract: A trapezoidal waveform synthesizer converts a digital phase error signal into a plurality of phase-separated trapezoidal analog waveforms. The trapezoidal waveform synthesizer includes an up/down counter that counts the positive and negative phase errors and generates a multi-bit, parallel digital counter output signal that indicates a cumulative current value of the phase errors. The counter output signal includes a least significant bit (LSB) portion and a most significant bit (MSB) portion. An upper PDM circuit converts the MSB portion of the output signal counter and a portion of the LSB portion of the counter output signal to a plurality of sets of serially-weighted multi-bit output signals. A lower PDM circuit converts the MSB and LSB portions of the counter output signal to a plurality of serially-weighted single-bit output signals. Each of the sets of multi-bit outputs and a corresponding one of the single-bit outputs are provided to an RC circuit that converts the digital signal to an analog voltage such that the waveform synthesizer provides a plurality of phase-separated trapezoidal waveforms.

Abstract translation: 梯形波形合成器将数字相位误差信号转换为多个相位分离的梯形模拟波形。 梯形波形合成器包括一个向上/向下计数器，用于对正和负相位误差进行计数，并产生指示相位误差的累积电流值的多位并行数字计数器输出信号。 计数器输出信号包括最低有效位（LSB）部分和最高有效位（MSB）部分。 上PDM电路将输出信号计数器的MSB部分和计数器输出信号的LSB部分的一部分转换成多组串行加权多位输出信号。 较低的PDM电路将计数器输出信号的MSB和LSB部分转换成多个串行加权的单位输出信号。 将多位输出和每个单位输出中的每一组提供给RC电路，该RC电路将数字信号转换为模拟电压，使得波形合成器提供多个相位分离的梯形波形。

公开(公告)号：US07979483B1

公开(公告)日：2011-07-12

申请号：US11506189

申请日：2006-08-16

Applicant: Hee Wong

Inventor： Hee Wong

IPC: G06F17/10

CPC classification number: G05B11/42

Abstract: A multiplexed digital proportional-integral-derivative filter receives error signal samples and operates in different states during sub-cycles of a single system cycle. A single multiplier and a single adder within the filter calculate at least portions of a proportional control signal, an integral control signal and a derivative control signal for one error signal sample during successive sub-cycles. The calculated control signal portions are aggregated to produce a filtered error signal for the respective error signal sample. The original resolution at lower cost, or increased resolution at the original cost, are achieved, as well as full programmability of loop gain with only negligible increase in loop latency.

Abstract translation: 复用的数字比例积分微分滤波器接收误差信号采样并在单个系统周期的子周期期间以不同的状态操作。 滤波器内的单个乘法器和单个加法器在连续的子周期期间计算一个误差信号采样的比例控制信号，积分控制信号和微分控制信号的至少一部分。 所计算的控制信号部分被聚合以产生用于相应误差信号样本的滤波误差信号。 以较低的成本或原始成本提高分辨率的原始分辨率，以及环路增益的全面可编程性，环路延迟增加可忽略不计。

公开(公告)号：US07930334B1

公开(公告)日：2011-04-19

申请号：US11731962

申请日：2007-04-02

Applicant: Hee Wong

Inventor： Hee Wong

IPC: G06F17/10

CPC classification number: G05B11/42

Abstract: Proportional, integral and derivative error gains within a proportional-integral-derivative filter are selected based on a magnitude of the error value and with successively higher gain values corresponding to larger ranges of error values. Coding of the error gains is selected based on one or more of: large code-dynamic-range to achieve good transient and quiescent responses; small code-step ratio to achieve smooth transitions between consecutive steps; large gain control range to satisfy the differing gain coverage requirements of the three proportional, integral and derivative error; positive and negative code symmetry with small step increment about zero; reservation of code space for dead band elimination; allocation of code space to prevent overflow/underflow during multiplying and bit-shifting; and minimum cost and power.

Abstract translation: 基于比例积分微分滤波器中的比例积分和微分误差增益是基于误差值的大小以及对应于较大范围误差值的连续较高增益值来选择的。 基于以下一个或多个选择误差增益的编码：大代码 - 动态范围以实现良好的瞬态和静态响应; 小代码步长比实现连续步骤之间的平滑过渡; 大增益控制范围满足三种比例，积分和微分误差的不同增益覆盖要求; 正，负码对称，小步增量约零; 预留死区消除代码空间; 分配代码空间，以防止在乘法和位移期间的溢出/下溢; 最低成本和最低功耗。

公开(公告)号：US07227476B1

公开(公告)日：2007-06-05

申请号：US11204297

申请日：2005-08-14

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H03M5/08

CPC classification number: H03M5/08

Abstract: Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.

Abstract translation: 用于数字脉宽调制器输出的抖动由脉冲浓度调制器提供，该脉冲密度调制器由加法器增加脉冲密度计数器并产生锁存到一加法器的进位信号，进位信号又增加一个相位分割周期 到来自数字脉冲宽度调制器的预定的一系列脉冲内的一个或多个所选脉冲中的每一个。 通过在系统时钟边沿之前的一个相位分割周期的时间触发脉冲的前沿，允许后沿被延长并且提供最小的等待时间延迟，所选脉冲被提前。

公开(公告)号：US06839551B1

公开(公告)日：2005-01-04

申请号：US09862048

申请日：2001-05-21

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H03D7/16 ,  H04B1/26 ,  H04B15/00

CPC classification number: H03D7/161

Abstract: There is disclosed a radio frequency (RF) demodulation circuit comprising: 1) a first RF mixer having a first input port for receiving an in-phase RF signal having a frequency of RF and a second input port for receiving an in-phase local oscillator (LO) signal having a frequency of LO, wherein LO is approximately equal to one-half of RF, and wherein the first RF mixer generates a first intermediate frequency (IF) signal having a frequency of LO; 2) a second RF mixer having a first input port for receiving an out-of-phase RF signal having a frequency of RF and a second input port for receiving an out-of-phase local oscillator (LO) signal having a frequency of LO, and wherein the second RF mixer generates a second intermediate frequency (IF) signal having a frequency of LO; and 3) a first signal combiner for combining the first and second IF signals to generate a composite IF signal, wherein the first signal combiner combines a first leakage signal from the first RF mixer and a second leakage signal from the second RF mixer such that the first and second leakage signals at least partially cancel each other to produce an output leakage signal that is less than either of the first and second leakage signals.

Abstract translation: 公开了一种射频（RF）解调电路，包括：1）第一RF混频器，具有用于接收具有RF频率的同相RF信号的第一输入端口和用于接收同相本机振荡器的第二输入端口 （LO）信号，其中LO大约等于RF的一半，并且其中第一RF混频器产生具有LO频率的第一中频（IF）信号; 2）具有用于接收具有RF频率的异相RF信号的第一输入端口和用于接收具有频率为LO的异相本地振荡器（LO））信号的第二输入端口的第二RF混频器， ，并且其中所述第二RF混频器产生具有LO频率的第二中频（IF）信号; 以及3）第一信号组合器，用于组合第一和第二IF信号以产生复合IF信号，其中第一信号组合器组合来自第一RF混频器的第一泄漏信号和来自第二RF混频器的第二泄漏信号，使得 第一和第二泄漏信号至少部分地彼此抵消以产生小于第一和第二泄漏信号中的任一个的输出泄漏信号。

公开(公告)号：US06452420B1

公开(公告)日：2002-09-17

申请号：US09865162

申请日：2001-05-24

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H03K1716

CPC classification number: H04L5/20 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/13062 ,  H01L2924/00

Abstract: A multi-dimensional differential signaling (MDDS) system is provided. A current loop is formed between N different communication lines and a corresponding differential is produced by loads coupled between the communication lines. The MDDS system may be two-dimensional or multi-dimensional. The number of communications lines chosen for the MDDS system affects the number of differential pairs in the system as well as the bits of information that may be transmitted. More than two states are provided by the MDDS system. For example, if three communication lines are used within the system, six states are provided. A star or delta load is used to produce the differential across the communication lines.

Abstract translation: 提供了一种多维差分信号（MDDS）系统。 在N个不同的通信线路之间形成电流回路，并且由通信线路之间耦合的负载产生相应的差分。 MDDS系统可以是二维或多维的。 为MDDS系统选择的通信线路数量会影响系统中差分对的数量以及可能传输的信息位。 MDDS系统提供了两个以上的状态。 例如，如果在系统内使用三条通信线路，则提供六种状态。 星形或三角形负载用于在通信线路之间产生差分。

公开(公告)号：US5351275A

公开(公告)日：1994-09-27

申请号：US729973

申请日：1991-07-15

Applicant: Hee Wong ,  Tsun-Kit Chin

Inventor： Hee Wong ,  Tsun-Kit Chin

IPC: H03L7/06 ,  H03H17/02 ,  H03L7/093 ,  H03L7/099 ,  H03D3/24

CPC classification number: H03L7/093 ,  H03L7/0991 ,  H03L2207/04

Abstract: A digital programmable loop filter for high frequency control systems applications utilizing a serial processing technique on pulse densities. The loop filter contains a proportional signal path and an integral signal path. A 4-time-slot sequencer time-multiplexes the serial proportional and integral signals to emulate a 1-pole/1-zero filter. An acquisition speed control circuit controls the acquisition time as well as step sizes of the scaler (proportional path) and the integrator (integral path) to provide loop variable programmability.

Abstract translation: 一种用于高频控制系统应用的数字可编程环路滤波器，利用脉冲密度的串行处理技术。 环路滤波器包含比例信号路径和积分信号路径。 4时隙定序器对串行比例和积分信号进行时间复用，以模拟1极/ 1 - 零滤波器。 采集速度控制电路控制采集时间以及缩放器（比例路径）和积分器（积分路径）的步长，以提供循环变量可编程性。

公开(公告)号：US5295079A

公开(公告)日：1994-03-15

申请号：US731963

申请日：1991-07-18

Applicant: Hee Wong ,  Tsun-Kit Chin

Inventor： Hee Wong ,  Tsun-Kit Chin

IPC: G01R31/28 ,  H03L7/06 ,  H03L7/08 ,  H03L7/099 ,  G01R23/02

CPC classification number: H03L7/0991 ,  G01R31/282

Abstract: A digital testing system providing for cost efficient comprehensive testing of very high frequency phase-locked loop performance parameters. The system tests PLL performance parameters both at integrated circuit level and communication board level. Cost efficiency of the testing system allows for volume testing by manufacturers.

Abstract translation: 数字测试系统，提供高频锁相环性能参数的成本效益综合测试。 该系统在集成电路级和通信板级测试PLL性能参数。 测试系统的成本效率允许制造商进行批量测试。

公开(公告)号：US5239561A

公开(公告)日：1993-08-24

申请号：US731138

申请日：1991-07-15

Applicant: Hee Wong ,  Tsun-Kit Chin

Inventor： Hee Wong ,  Tsun-Kit Chin

IPC: H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H04L7/033

CPC classification number: H03L7/0991 ,  H03L7/085 ,  H04L7/033

Abstract: A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream. The integrated information is converted by the phase error processor once during each N-clock cycle period into a one-bit Up/Down signal that is then used to either advance or retard the output phase of the PLL's digitally controlled oscillator. The phase error processor also detects when the density of edges in the incoming data stream falls below a minimum allowed level, and generates a "data valid" signal indicating whether the Up/Down signal are valid.

公开(公告)号：US4873700A

公开(公告)日：1989-10-10

申请号：US108718

申请日：1987-10-14

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H04B3/06 ,  H04L25/03 ,  H04L25/06 ,  H04L25/30

CPC classification number: H04L25/063 ,  H04L25/03038

Abstract: An auto-threshold circuit in accordance with the present invention comprises a full-wave peak sensor for accurately estimating slice levels for input signal detection. The peak sensor is qualified such that the auto-threshold circuit does not track an input signal with no modulation. The input signal is windowed with a phase-locked-loop so that the peak sensor is coherent to the input signal, causing the circuit to be insensitive to noise spikes or input distortion outside the window. The auto-threshold circuit includes a digital loop filter which receives the output from an auto-threshold controller and generates a corresponding binary signal which is converted by a digital Sigma/delta modulator to a single bit pulse density modulated signal having a predetermined sampling frequency. An adaptive equalizer in accordance with the present invention shares the auto-threshold slicing signal for generating its error feedback signal. The adaptive equalizer comprises a frequency selector which generates an output signal in response to the input signal and the feedback signal. As stated above, a threshold comparator slices the equalizer output at predetermined levels. A controller receives the comparator output and provides a controller output representative of the voltage level of the comparator output. A digital filter is then utilized to generate a corresponding binary signal as the feedback signal to the frequency selector. The adaptive equalizer is operable at more than one speed.