公开(公告)号：US20160227945A1

公开(公告)日：2016-08-11

申请号：US15011692

申请日：2016-02-01

Applicant: Kwok Hee Wong

Inventor： Kwok Hee Wong

IPC: A47G1/06 ,  B31D5/04

CPC classification number: A47G1/0633 ,  B31D5/04

Abstract: A blank for forming a one-piece picture frame with picture includes a blank body having front and rear surfaces, a central rectangular picture portion formed thereon with a picture on the front surface. The blank further includes four wing portions extending from the four margins of the rectangular picture portion and the four wing portions are foldable into four rectangular tubular frame sections. Twelve locking mechanisms are used to lock the four frame sections in a folded position. A method of forming the picture frame with picture is also disclosed.

Abstract translation: 用于形成具有图像的一体式相框的坯料包括具有前表面和后表面的坯体，在其上形成有前表面上的图片的中心矩形图像部分。 坯料还包括从矩形图像部分的四个边缘延伸的四个翼部分，并且四个翼部分可折叠成四个矩形管状框架部分。 使用十二个锁定机构将四个框架部分锁定在折叠位置。 还公开了一种用图像形成图像帧的方法。

公开(公告)号：US08238414B1

公开(公告)日：2012-08-07

申请号：US11904025

申请日：2007-09-25

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation time for the proportional-integral-derivative filter is predicted based on an average for previous digital pulse width modulator outputs, computed within the integral path for the previous loop iteration. A margin is added to accommodate transient conditions accelerating the trailing edge of the digital pulse width modulator output, either fixed or variable depending on the previous iteration pulse width.

Abstract translation: 功率切换器等内的数字控制回路包括滑动误差采样器脉冲宽度调制定时，可相对于数字脉宽调制器输出后沿可变地设定时钟周期数，用于加载用于滤波器的控制变量。 基于对先前循环迭代的积分路径中计算的先前数字脉宽调制器输出的平均值，预测比例积分微分滤波器的计算时间。 加上余量以适应加速数字脉冲宽度调制器输出的后沿的瞬态条件，固定或可变取决于先前的迭代脉冲宽度。

公开(公告)号：US07616052B1

公开(公告)日：2009-11-10

申请号：US10379368

申请日：2003-03-04

Applicant: Shu-Ing Ju ,  Hee Wong

Inventor： Shu-Ing Ju ,  Hee Wong

IPC: H03K5/00

CPC classification number: H03H21/0001

Abstract: Adjustable gain circuits (AGCs) within serial filter stages are initialized to maximum gain. The output of each AGC is then sampled and converted to digital representation for use by control logic in setting the gain for the respective AGC. The gain adjustment decision for each AGC is performed in one shot, sequentially backwards from the last AGC, such that gain may be adapted simply and quickly within a number of cycles equal to the number of AGCs. Performance is enhanced by a fast-adapting cell in which capacitances are switched into the input path and feedback loop of an amplifier to reduce direct current gain within the transfer function through charge sharing dividing down the output voltage.

Abstract translation: 串行滤波器级中的可调增益电路（AGC）被初始化为最大增益。 然后，每个AGC的输出被采样并转换成数字表示，供控制逻辑用于设定相应AGC的增益。 每个AGC的增益调整决定一次性执行，从最后的AGC顺序地向后执行，使得增益可以在等于AGC的数量的数量周期内简单且快速地进行调整。 通过快速适配单元增强性能，其中电容被切换到放大器的输入路径和反馈环路，以通过分压输出电压的电荷共享来减小传递函数内的直流增益。

公开(公告)号：US20090002040A1

公开(公告)日：2009-01-01

申请号：US11964824

申请日：2007-12-27

Applicant: Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

Inventor： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

IPC: H03L7/06

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

Abstract: A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

Abstract translation: 一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号 相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位 输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

公开(公告)号：US07336938B1

公开(公告)日：2008-02-26

申请号：US10464424

申请日：2003-06-18

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H04B1/10

CPC classification number: H03D7/14 ,  H03D2200/0086

Abstract: Rejection of local oscillator alias response is provided in a mixing circuit by (1) a switching mixer producing an output that changes at least twice between two states (e.g., high-low-high or low-high-low) during each local oscillator period, and (2) a charge integrator integrating current output from the switching mixer over the local oscillator period. The switching mixer and charge integrator produce a sampled data format, double sideband signal with serial cancellation of the switching mixer's alias responses. An extension unit connected in series with the switching mixer and charge integrator, and implementing a transform function computing a difference between consecutive samples, produces a cascading effect with the switching mixer and charge integrator, optionally producing additional nulls suppressing alias response at frequencies near the local oscillator frequency. A harmonic gating circuit between the switching mixer and charge integrator, controlled at a multiple of the local oscillator frequency, suppresses harmonic responses of the switching mixer.

Abstract translation: 在混合电路中通过以下方式提供本地振荡器别名响应的拒绝：（1）在每个本地振荡器周期期间产生在两个状态（例如，高低或高或低 - 低 - 低）之间改变至少两次的输出的开关混频器 ，和（2）在本地振荡器周期内积分从开关混频器输出的电流的电荷积分器。 开关混频器和电荷积分器产生采样数据格式，双边带信号，串行取消开关混频器的别名响应。 与开关混频器和电荷积分器串联连接的扩展单元，并且实现计算连续样本之间的差异的变换函数，与开关混频器和电荷积分器产生级联效应，可选地产生在本地附近的频率处抑制别名响应的附加零点 振荡器频率。 开关混频器和电荷积分器之间的谐波门控电路控制在本地振荡器频率的倍数，可以抑制开关混频器的谐波响应。

公开(公告)号：US07212588B1

公开(公告)日：2007-05-01

申请号：US10081668

申请日：2002-02-20

Applicant: Hee Wong ,  Shu-Ing Ju

Inventor： Hee Wong ,  Shu-Ing Ju

IPC: H04L27/00 ,  H04L7/00 ,  H04B7/216 ,  H04B1/00

CPC classification number: H04B1/1027 ,  H03D3/007 ,  H03D7/161

Abstract: A radio frequency (RF) receiver comprising: 1) a local oscillator (LO) circuit capable of receiving a local oscillator (LO) reference signal having frequency, LO, and a double sideband (DSB) clock signal having a frequency, DSB, and generating therefrom an in-phase product signal of the LO reference signal and the DSB clock signal in which a polarity of the LO reference signal is reversed at the DSB frequency of the DSB clock signal; and 2) a first radio frequency (RF) mixer having a first input port capable of receiving the in-phase product signal from the LO circuit and a second input port capable of receiving a modulated radio frequency (RF) signal, wherein the first RF mixer generates a first downconverted output signal.

Abstract translation: 一种射频（RF）接收机，包括：1）能够接收具有频率LO的本地振荡器（LO）参考信号和具有频率DSB的双边带（DSB）时钟信号的本地振荡器（LO）电路， 从而产生LO参考信号和DSB时钟信号的同相产品信号，其中LO参考信号的极性在DSB时钟信号的DSB频率处反向; 以及2）第一射频（RF）混频器，具有能够接收来自LO电路的同相产品信号的第一输入端口和能够接收调制射频（RF）信号的第二输入端口，其中第一RF 混频器产生第一个下变频输出信号。

公开(公告)号：US06959179B1

公开(公告)日：2005-10-25

申请号：US10068293

申请日：2002-02-06

Applicant: Hee Wong ,  Shu-Ing Ju

Inventor： Hee Wong ,  Shu-Ing Ju

IPC: H04B1/26 ,  H04B1/30

CPC classification number: H04B1/30

Abstract: A RF down/up-conversion circuit comprising: 1) a local oscillator chopping circuit comprising: a) a frequency divider circuit for receiving a first local oscillator (LO) signal having a frequency of LO and generating a frequency-divided second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and b) a multiplier for receiving the first and second LO signals and generating a product signal of the first and second LO signals; and 2) a differential radio frequency (RF) mixer having a first differential input port for receiving the product signal from the multiplier and a second differential input port for receiving a first differential modulated radio frequency (RF) signal and a second differential modulated radio frequency (RF) signal, wherein the differential RF mixer generates a differential output signal.

Abstract translation: 1.一种RF下降/上变频电路，包括：1）本地振荡器斩波电路，包括：a）分频器电路，用于接收具有LO频率的第一本地振荡器（LO）信号，并产生分频的第二本地振荡器 LO）信号，其具有LO / N的频率并与第一LO信号同步; 以及b）用于接收第一和第二LO信号并产生第一和第二LO信号的乘积信号的乘法器; 以及2）差分射频（RF）混频器，具有用于从乘法器接收乘积信号的第一差分输入端口和用于接收第一差分调制射频（RF）信号和第二差分调制射频的第二差分输入端口 （RF）信号，其中差分RF混频器产生差分输出信号。

公开(公告)号：US06876844B1

公开(公告)日：2005-04-05

申请号：US09895935

申请日：2001-06-29

Applicant: Hee Wong

Inventor： Hee Wong

IPC: H04B1/28 ,  H04B1/38

CPC classification number: H04B1/0007 ,  H04B1/0003 ,  H04B1/28

Abstract: A radio frequency (RF) demodulation circuit comprising: 1) a radio frequency (RF) mixer having a first input port capable of receiving an incoming RF signal having a frequency of RF and a second input port capable of receiving a first local oscillator (LO) signal having a frequency of LO, wherein the RF mixer generates a first intermediate frequency (IF) signal having a frequency of IF; 2) a frequency divider circuit capable of receiving the first LO signal having the frequency of LO and generating therefrom a second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and 3) an intermediate frequency (IF) mixer having a first input port capable of receiving the first IF signal and a second input port capable of receiving the second LO signal having the frequency of LO/N, and wherein the IF mixer generates a baseband output signal.

Abstract translation: 一种射频（RF）解调电路，包括：1）射频（RF）混频器，具有能够接收具有RF频率的输入RF信号的第一输入端口和能够接收第一本地振荡器（LO ）信号，其中所述RF混频器产生具有IF频率的第一中频（IF）信号; 2）能够接收具有LO频率的第一LO信号并从其产生具有LO / N频率并与第一LO信号同步的第二本地振荡器（LO）信号的分频器电路; 以及3）具有能够接收第一IF信号的第一输入端口和能够接收具有LO / N频率的第二LO信号的第二输入端口的中频（IF）混频器，并且其中IF混频器产生基带 输出信号。

公开(公告)号：US5943379A

公开(公告)日：1999-08-24

申请号：US873118

申请日：1997-06-11

Applicant: Hee Wong ,  Gabriel Ming-Yu Li

Inventor： Hee Wong ,  Gabriel Ming-Yu Li

IPC: H03L7/08 ,  H03L7/089 ,  H03L7/099 ,  H03D3/24 ,  H04L7/00 ,  H04L25/36 ,  H04L25/40

CPC classification number: H03L7/0995 ,  H03L7/08 ,  H03L7/089

Abstract: A trapezoidal waveform synthesizer converts a digital phase error signal into a plurality of phase-separated trapezoidal analog waveforms. The trapezoidal waveform synthesizer includes an up/down counter that counts the positive and negative phase errors and generates a multi-bit, parallel digital counter output signal that indicates a cumulative current value of the phase errors. The counter output signal includes a least significant bit (LSB) portion and a most significant bit (MSB) portion. An upper PDM circuit converts the MSB portion of the output signal counter and a portion of the LSB portion of the counter output signal to a plurality of sets of serially-weighted multi-bit output signals. A lower PDM circuit converts the MSB and LSB portions of the counter output signal to a plurality of serially-weighted single-bit output signals. Each of the sets of multi-bit outputs and a corresponding one of the single-bit outputs are provided to an RC circuit that converts the digital signal to an analog voltage such that the waveform synthesizer provides a plurality of phase-separated trapezoidal waveforms.

Abstract translation: 梯形波形合成器将数字相位误差信号转换为多个相位分离的梯形模拟波形。 梯形波形合成器包括一个向上/向下计数器，用于对正和负相位误差进行计数，并产生指示相位误差的累积电流值的多位并行数字计数器输出信号。 计数器输出信号包括最低有效位（LSB）部分和最高有效位（MSB）部分。 上PDM电路将输出信号计数器的MSB部分和计数器输出信号的LSB部分的一部分转换成多组串行加权多位输出信号。 较低的PDM电路将计数器输出信号的MSB和LSB部分转换成多个串行加权的单位输出信号。 将多位输出和每个单位输出中的每一组提供给RC电路，该RC电路将数字信号转换为模拟电压，使得波形合成器提供多个相位分离的梯形波形。

公开(公告)号：US5841810A

公开(公告)日：1998-11-24

申请号：US791382

申请日：1997-01-30

Applicant: Hee Wong ,  Abhijit Phanse

Inventor： Hee Wong ,  Abhijit Phanse

IPC: H04B3/14 ,  H03H7/30 ,  H03K5/159

CPC classification number: H04B3/145 ,  H04L25/03885

Abstract: An adaptive equalizer for adaptively equalizing a data signal received via a communications path having a signal loss magnitude which increases with signal frequency includes multiple, serially coupled adaptive filter stages. The input data signal is successively filtered and magnitude weighted by successive adaptive filter circuits in accordance with corresponding, respective adaptation control signals. The frequency domain ratio of output signals to corresponding input signals for each adaptive filter circuit represents a corresponding, respective adaptive filter transfer function. An equalizer controller, in accordance with a single equalization control signal, generates the multiple, individual adaptation control signals. The product of all of the adaptive filter transfer functions is an approximate inverse of the transfer function of the input data signal communications path, with each individual adaptive filter transfer function being an approximate inverse of a transfer function which corresponds to a portion of the input data signal communications path. The magnitude of the equalization control signal corresponds to the transfer function of the input data signal communications path, while the magnitude of each adaptation control signal corresponds to one of the transfer function corresponding to a portion of the input data signal communications path.

Abstract translation: 用于自适应均衡经由具有随信号频率增加的信号损耗大小的通信路径接收的数据信号的自适应均衡器包括多个串联耦合的自适应滤波器级。 输入数据信号根据相应的各自的自适应控制信号被连续滤波和连续的自适应滤波电路的幅度加权。 每个自适应滤波电路的输出信号与相应输入信号的频域比表示相应的各自的自适应滤波器传递函数。 均衡器控制器根据单个均衡控制信号产生多个单独的自适应控制信号。 所有自适应滤波器传递函数的乘积是输入数据信号通信路径的传递函数的近似逆，每个单独的自适应滤波器传递函数是对应于输入数据的一部分的传递函数的近似逆 信号通信路径。 均衡控制信号的幅度对应于输入数据信号通信路径的传递函数，而每个自适应控制信号的幅度对应于与输入数据信号通信路径的一部分相对应的传递函数之一。