-
1.发明授权Compensation circuit and method for reducing intersymbol interference products caused by signal transmission via dispersive media 有权补偿电路和减少信号传输通过色散介质引起的符号间干扰产物的方法公开(公告)号：US08050318B2
公开(公告)日：2011-11-01
申请号：US11553019
申请日：2006-10-26
Applicant: Abhijit Phanse , Abhijit G. Shanbhag
Inventor： Abhijit Phanse , Abhijit G. Shanbhag
CPC classification number: H04L25/03057 , H04B10/6971 , H04L25/03038 , H04L25/03878 , H04L2025/03624 , H04L2025/03656 , H04L2025/037
Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
Abstract translation: 用于减少与通过信号传输介质接收的检测数据信号相对应的电数据信号内的ISI产品的补偿电路和方法对电数据信号内的各个ISI产品引入不同的补偿效果。 检测到的数据信号中对应于这种ISI产品的不同数据信号分量可以被选择性和单独地补偿，从而产生补偿数据信号，其中基本上去除了这些单个数据信号分量中的每一个。 可以根据需要补偿单个数据信号分量或数据信号分量的选定组合。
-
公开(公告)号：US07627031B2
公开(公告)日：2009-12-01
申请号：US11186241
申请日：2005-07-21
Applicant: Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Edem Ibragimov , Fabian Giroud
Inventor： Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Edem Ibragimov , Fabian Giroud
IPC: H03H7/30
CPC classification number: H04L7/0062 , H04L7/0029 , H04L25/03057 , H04L2025/03503
Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
Abstract translation: 一种用于自适应地引入与数据符号判定电路的信号等待时间相关的补偿信号延迟的装置和方法。 自适应定时控制电路，包括实现为具有相关抽头系数的抽头延迟线的内插混频器，自适应地和基本上匹配数据判决电路的等待时间以在自适应均衡器内使用，从而最小化这样的均方误差 决策电路。 该自适应等待时间用于产生反馈误差信号，反馈误差信号又可由前馈均衡器用于动态调整其自适应滤波器抽头系数。
-
公开(公告)号：US07130366B2
公开(公告)日：2006-10-31
申请号：US10290674
申请日：2002-11-08
Applicant: Abhijit Phanse , Abhijit G. Shanbhag
Inventor： Abhijit Phanse , Abhijit G. Shanbhag
IPC: H04B1/00
CPC classification number: H04L25/03057 , H04B10/6971 , H04L25/03038 , H04L25/03878 , H04L2025/03624 , H04L2025/03656 , H04L2025/037
Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
-
公开(公告)号：US06223325B1
公开(公告)日：2001-04-24
申请号：US09076186
申请日：1998-05-12
Applicant: Wong Hee , Abhijit Phanse
Inventor： Wong Hee , Abhijit Phanse
IPC: G06F1100
CPC classification number: H04L1/20
Abstract: A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT3 Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.
Abstract translation: 数据信号峰值误差检测器，用于监测和检测多级数据信号（例如MLT3以太网信号）的峰值电平中的不期望的移位。 信号分片电路产生两个信号：数据峰值检测信号识别数据信号峰值的出现，并且当输入数据信号电平已经转变到超过之前的中间值和峰值（例如，正或负）信号电平 ; 并且数据峰值误差信号识别数据信号峰值误差的出现，并且当输入数据信号电平已经转变超过对应于先前峰值信号电平的值时被断言。 数据峰值检测信号的断言通过计数器启动计数序列。 对计数序列进行解码以产生一个或多个信号脉冲，每个信号脉冲在确定第一数据峰值信号之后的相应时间处被提供，并且识别数据峰值误差信号的有效状态。
-
公开(公告)号：US5940442A
公开(公告)日：1999-08-17
申请号：US791381
申请日：1997-01-30
Applicant: Hee Wong , Abhijit Phanse
Inventor： Hee Wong , Abhijit Phanse
CPC classification number: H04L25/062 , H04B3/04
Abstract: A high speed data receiver for recovering binary or MLT3 encoded data which has been received via a cable. An adaptive equalizer provides signal gain which increases with frequency and adapts according to the length of the cable. Control over such adaptive equalizing is achieved by monitoring the peak-to-peak amplitude, amplitude peaks and differences between amplitude peaks of the equalized data signal during defined time intervals. Baseline restoration and dynamic data slicing are also provided.
Abstract translation: 用于恢复已经通过电缆接收的二进制或MLT3编码数据的高速数据接收器。 自适应均衡器提供随频率增加的信号增益，并根据电缆的长度进行调整。 通过在规定的时间间隔期间监视均衡数据信号的峰 - 峰幅度，振幅峰值和振幅峰值之间的差异来实现对这种自适应均衡的控制。 还提供了基线恢复和动态数据切片。
-
Patent Agency Ranking6.发明授权Digital to analog converter for generating distributive analog control signals utilizing digital signal generator and control signal generator 失效数模转换器，用于利用数字信号发生器和控制信号发生器产生分布式模拟控制信号
公开(公告)号：US5784019A
公开(公告)日：1998-07-21
申请号：US791367
申请日：1997-01-30
Applicant: Hee Wong , Abhijit Phanse
Inventor： Hee Wong , Abhijit Phanse
CPC classification number: H03M1/662
Abstract: A digital-to-analog converter for converting a multiple bit digital input signal into multiple representative analog output signals includes a pulse density modulator, a logic controller, signal selection logic circuits and resistive-capacitive lowpass output filters. The pulse density modulator receives the N-M least significant bits of an N-bit digital input signal and in accordance therewith generates a pulse density modulated digital signal with a pulse density corresponding to a digital count of such N-M least significant bits. The logic controller receives the M most significant bits of the N-bit digital input signal and in accordance therewith generates multiple pairs of digital control signals. Each of the signal selection logic circuits receives the pulse density modulated digital signal and a respective pair of the digital control signals and in accordance therewith provides a respective one of a number of digital output signals. Together, each pair of digital control signals determines whether one of them or the pulse density modulated digital signal is provided as the respective digital output signal. The output filters lowpass filter the digital output signals to convert them to analog signals. The resulting analog signals represent a digital count of the original digital signal bits.
Abstract translation: 用于将多位数字输入信号转换为多个代表性模拟输出信号的数模转换器包括脉冲密度调制器，逻辑控制器，信号选择逻辑电路和电阻电容低通滤波器。 脉冲浓度调制器接收N位数字输入信号的N-M个最低有效位，并且根据其生成脉冲密度调制的数字信号，脉冲密度对应于这样的N-M个最低有效位的数字计数。 逻辑控制器接收N位数字输入信号的M个最高有效位，并根据其产生多对数字控制信号。 每个信号选择逻辑电路接收脉冲密度调制数字信号和相应的一对数字控制信号，并根据其提供多个数字输出信号中的相应一个。 一对数字控制信号一起确定它们中的一个或脉冲浓度调制的数字信号是否被提供为相应的数字输出信号。 输出滤波器对数字输出信号进行低通滤波，将其转换为模拟信号。 所得到的模拟信号表示原始数字信号位的数字计数。
-
7.发明授权Adaptive signal equalizer with adaptive error timing and precursor/postcursor configuration control 有权自适应信号均衡器，具有自适应误差定时和前置/后端配置控制公开(公告)号：US07266145B2
公开(公告)日：2007-09-04
申请号：US10321876
申请日：2002-12-17
Applicant: Venugopal Balasubramonian , Jishnu Bhattacharjee , Edem Ibragimov , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Qian Yu
Inventor： Venugopal Balasubramonian , Jishnu Bhattacharjee , Edem Ibragimov , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Qian Yu
CPC classification number: H04L25/03057 , H03H21/0012 , H03H2021/0096 , H04L7/0029 , H04L7/0062 , H04L7/0079 , H04L2025/0349 , H04L2025/03611
Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.
Abstract translation: 一种具有前馈滤波器的自适应信号均衡器，其中反馈误差信号和相应的输入数据信号在时间上使用信号插值动态对准，此外，控制前驱/后沿滤波器抽头配置，由此产生更多的自适应滤波器抽头系数信号， 显着改善和鲁棒的信号均衡。
-
公开(公告)号：US06952132B2
公开(公告)日：2005-10-04
申请号：US10724444
申请日：2003-11-26
Applicant: Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
Inventor： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
Abstract: Systems and methods provide automatic gain control, such as by employing analog and digital techniques. For example, overall gain may be controlled through coarse and fine control signals provided to gain stages, with the overall gain monitored via a power detector circuit.
-
公开(公告)号：US20050104158A1
公开(公告)日：2005-05-19
申请号：US10718501
申请日：2003-11-19
Applicant: Jishnu Bhattacharjee , Madabusi Govindarajan , Debanjan Mukherjee , Abhijit Phanse , Prashant Choudhary
Inventor： Jishnu Bhattacharjee , Madabusi Govindarajan , Debanjan Mukherjee , Abhijit Phanse , Prashant Choudhary
IPC: H01L21/02 , H01L23/522 , H01L29/00
CPC classification number: H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
Abstract: An inductor for an integrated circuit made of a plurality of stacked, electrically coupled, metal layers. Each metal layer includes an inductor formed of a spiral pattern, which except for the top and bottom inductors, are electrically coupled to the spiral inductor formed on the metal layer above and below with an electrical path or via formed between each metal layer. The top and bottom inductors are electrically coupled to the inductor directly below and above, respectively.
Abstract translation: 一种用于由多个堆叠的电耦合的金属层制成的集成电路的电感器。 每个金属层包括由螺旋图案形成的电感器，除了顶部和底部电感器之外，通过在每个金属层之间形成的电路径或通孔电连接到形成在金属层上的螺旋电感器上方和下方。 顶部和底部电感器分别电连接到电感器上方。
-
10.发明授权Distributive encoder for encoding error signals which represent signal peak errors in data signals for correcting erroneous signal baseline conditions 有权用于编码误差信号的分布式编码器，其表示用于校正错误信号基线条件的数据信号中的信号峰值误差
公开(公告)号：US6125470A
公开(公告)日：2000-09-26
申请号：US176633
申请日：1998-10-22
Applicant: Wong Hee , Abhijit Phanse
Inventor： Wong Hee , Abhijit Phanse
CPC classification number: H04L25/03019 , H04L2025/03356
Abstract: A digital signal error detection circuit and method for identifying interruptions in respective occurrences of opposing signal states of an equalized digital data signal. Signal level status signals are monitored during a specified monitoring time period to determine whether the data signal being monitored contains at least one positive data pulse and at least one negative data pulse. If this condition is not met, then an error signal is generated for use in correcting the equalization of the original data signal.
Abstract translation: 一种数字信号误差检测电路和方法，用于识别均衡数字数据信号的相对信号状态的相应出现中的中断。 在指定的监视时间段期间监视信号电平状态信号，以确定被监视的数据信号是否包含至少一个正数据脉冲和至少一个负数据脉冲。 如果不满足该条件，则产生用于校正原始数据信号的均衡的误差信号。
-
-
-
-
-
-
-
-
-
Search Results
52
records
(took 0.025 seconds)
