公开(公告)号：US06223325B1

公开(公告)日：2001-04-24

申请号：US09076186

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: G06F1100

CPC classification number: H04L1/20

Abstract: A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT3 Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.

Abstract translation: 数据信号峰值误差检测器，用于监测和检测多级数据信号（例如MLT3以太网信号）的峰值电平中的不期望的移位。 信号分片电路产生两个信号：数据峰值检测信号识别数据信号峰值的出现，并且当输入数据信号电平已经转变到超过之前的中间值和峰值（例如，正或负）信号电平 ; 并且数据峰值误差信号识别数据信号峰值误差的出现，并且当输入数据信号电平已经转变超过对应于先前峰值信号电平的值时被断言。 数据峰值检测信号的断言通过计数器启动计数序列。 对计数序列进行解码以产生一个或多个信号脉冲，每个信号脉冲在确定第一数据峰值信号之后的相应时间处被提供，并且识别数据峰值误差信号的有效状态。

公开(公告)号：US6125470A

公开(公告)日：2000-09-26

申请号：US176633

申请日：1998-10-22

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: G06F11/00 ,  H03N13/00

CPC classification number: H04L25/03019 ,  H04L2025/03356

Abstract: A digital signal error detection circuit and method for identifying interruptions in respective occurrences of opposing signal states of an equalized digital data signal. Signal level status signals are monitored during a specified monitoring time period to determine whether the data signal being monitored contains at least one positive data pulse and at least one negative data pulse. If this condition is not met, then an error signal is generated for use in correcting the equalization of the original data signal.

Abstract translation: 一种数字信号误差检测电路和方法，用于识别均衡数字数据信号的相对信号状态的相应出现中的中断。 在指定的监视时间段期间监视信号电平状态信号，以确定被监视的数据信号是否包含至少一个正数据脉冲和至少一个负数据脉冲。 如果不满足该条件，则产生用于校正原始数据信号的均衡的误差信号。

公开(公告)号：US06259302B1

公开(公告)日：2001-07-10

申请号：US09176784

申请日：1998-10-22

Applicant: Abhijit Phanse ,  Wong Hee

Inventor： Abhijit Phanse ,  Wong Hee

IPC: G06G712

CPC classification number: H04B3/145

Abstract: A gain controller for a signal mixer in which consistent circuit gain is maintained by using transistors in the gain control and signal mixing stages with equal corresponding device dimensions and by using a differential gain control voltage with inverse and noninverse differential voltage phases which individually track variations in the dc bias currents used to power the gain control and signal mixing stages. This provides a gain factor which is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. Such a gain controller provides a self-compensating gain control signal which is based upon a variable gain control factor and tracks variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures by tracking variations in the dc biasing used to power the gain control and signal mixing stages. Such tracking of the biasing by the gain control advantageously provides for an increased dynamic range.

Abstract translation: 一种用于信号混合器的增益控制器，其中通过在增益控制和信号混合阶段中使用晶体管来维持一致的电路增益，具有相等的相应器件尺寸，并且通过使用差分增益控制电压，该差分增益控制电压具有反向和非反相差分电压相位， 用于为增益控制和信号混合阶段供电的直流偏置电流。 这提供了由于电路制造过程和工作电压和温度的变化而与电路操作的变化无关的增益因子。 这种增益控制器提供基于可变增益控制因子的自补偿增益控制信号，并且通过跟踪用于为电源供电的直流偏置中的变化而跟踪由于电路制造过程和工作电压和温度的变化而跟踪电路操作中的变化 增益控制和信号混合阶段。 通过增益控制对偏置的这种跟踪有利地提供了增加的动态范围。

公开(公告)号：US6167080A

公开(公告)日：2000-12-26

申请号：US76260

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03038 ,  H04L25/03885

Abstract: A closed feedback loop controls the adaptive equalization of an incoming data signal received via a cable. Detected signal information about the positive and negative peaks of the incoming data signal during different windows in time is processed to generate a set of adaptive equalization control signals which identify differences, if any, between the positive and negative peaks of the present data signal and those which are desired. These equalization control signals control an input signal equalization circuit which adaptively adjusts the waveshape of the present data signal to bring it into conformance with the desired waveshape.

Abstract translation: 闭合反馈环路控制通过电缆接收的输入数据信号的自适应均衡。 处理在不同窗口期间输入数据信号的正峰值和负峰值的检测信号信息，以生成一组自适应均衡控制信号，该信号识别当前数据信号的正峰值和负峰值之间的差异（如果有的话） 这是所需的。 这些均衡控制信号控制输入信号均衡电路，其自适应地调整当前数据信号的波形以使其符合期望的波形。

公开(公告)号：US06363111B1

公开(公告)日：2002-03-26

申请号：US09076256

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: H04B346

CPC classification number: H04B17/327

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract translation: 闭合反馈环路控制输入数据信号的切片或检测。 处理关于输入数据信号的正峰值和负峰值的检测信号信息，以产生正和负峰值参考信号，其作为用于建立发生信号切片的阈值的参考信号电平。

公开(公告)号：US06301309B1

公开(公告)日：2001-10-09

申请号：US09076425

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: H04L2534

CPC classification number: H04L25/03885 ,  H04L25/0292 ,  H04L25/061 ,  H04L25/4925

Abstract: A signal gating controller for recovering true data signal pulses while gating out false data signal pulses which are generated and prevent convergence when recovering a multilevel data signal, such as an MLT3 Ethernet signal, which has been severely over-equalized. A signal slicing circuit generates two data peak signals: one data peak signal identifies occurrences of positive data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and positive peak signal levels; the other data peak signal identifies occurrences of negative data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and negative peak signal levels. A signal gating control circuit sequentially latches such data peak signals to produce two gating control signals. Logical combinations of such gating control and data peak signals produce gated signals in which the true data peak signal pulses remain while the false data peak signal pulses due to severe over-equalization of the incoming data signal are removed.

Abstract translation: 一种信号选通控制器，用于在选择产生的伪数据信号脉冲时，恢复真实数据信号脉冲，并在恢复已经严重过度均衡的MLT3以太网信号等多级数据信号时防止收敛。 信号分片电路产生两个数据峰值信号：一个数据峰值信号识别正数据信号峰值的出现，并且当输入数据信号电平已经转变到超过前一个零和正峰值信号电平之间的值时被断言; 另一个数据峰值信号识别负数据信号峰值的出现，并且当输入数据信号电平已经转变到超过前一个零和负峰值信号电平之间的值时被断言。 信号门控控制电路顺序地锁存这样的数据峰值信号以产生两个选通控制信号。 这种选通控制和数据峰值信号的逻辑组合产生门控信号，其中真实数据峰值信号脉冲保持，而由于输入数据信号的严重过均衡而导致的错误数据峰值信号脉冲被去除。

公开(公告)号：US6084466A

公开(公告)日：2000-07-04

申请号：US176783

申请日：1998-10-22

Applicant: Abhijit Phanse ,  Wong Hee

Inventor： Abhijit Phanse ,  Wong Hee

IPC: H03F3/00 ,  G06G7/12 ,  G08C13/00 ,  H03G3/30 ,  H04B3/36

CPC classification number: H03G3/001 ,  H03F3/45197 ,  H03G1/0029 ,  H04B3/04

Abstract: A mixing circuit for combining biasing and signals using a selectively variable signal gain which is independent of the biasing and using biasing which is independent of the selectively variable signal gain. A Gilbert cell is used to multiply a differential control voltage, which represents a normalized signal gain factor, with input currents which include biasing components and input signal components. The resultant output current includes a bias component which is independent of the differential control voltage and a signal component which is independent of the input current biasing components. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage.

Abstract translation: 一种混合电路，用于使用与选择性可变信号增益无关的偏置和使用偏置独立的选择性可变信号增益来组合偏置和信号。 吉尔伯特单元用于将表示归一化信号增益因子的差分控制电压与包括偏置分量和输入信号分量的输入电流相乘。 所得到的输出电流包括独立于差分控制电压的偏置分量和独立于输入电流偏置分量的信号分量。 增益因子具有在零和单位之间的值，其相对于差分输入控制电压而变化。

公开(公告)号：US6044489A

公开(公告)日：2000-03-28

申请号：US076261

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: G11B27/00 ,  H04L25/06

CPC classification number: H04L25/063

Abstract: A data signal baseline error detector for monitoring and detecting undesired shifts in the baseline, or other intermediate level, of a multilevel data signal, such as an MLT3 Ethernet signal, as well as correcting for DC or low frequency offsets within a data receiving system. A signal slicing circuit generates two control signals: a data baseline signal indicates whether the data signal level is above or below a predetermined baseline reference level; and a data zero signal indicates when the data signal is in its zero, i.e., baseline, state and, when asserted, initiates a count sequence by a counter. The count sequence is decoded and the resulting decoded pulse sequence is gated in accordance with the data zero signal. Such pulses can be used to control a sampling circuit for sampling the data baseline signal or, alternatively, for sampling the data signal directly while in its zero state. The gating of the decoded pulses is done in such a manner as to prevent the outputting of decoded pulses which would otherwise occur too closely to the rising or falling edge of the data signal as it transitions away from its zero state, thereby ensuring that any signal sampling done occurs only during the true zero, or baseline, state of the data signal and not during any periods of signal level transitions.

Abstract translation: 数据信号基准误差检测器，用于监测和检测诸如MLT3以太网信号的多电平数据信号的基线或其他中间电平中的不期望的移位，以及校正数据接收系统内的DC或低频偏移。 信号分片电路产生两个控制信号：数据基线信号指示数据信号电平是否高于或低于预定的基线参考电平; 并且数据零信号指示数据信号何时为零，即基线状态，并且当被断言时，由计数器发起计数序列。 对计数序列进行解码，并根据数据零信号对结果解码的脉冲序列进行门控。 这样的脉冲可以用于控制采样电路以对数据基线信号进行采样，或者替代地，用于在处于零状态时直接采样数据信号。 解码脉冲的门控以这样的方式完成，即防止输出解码的脉冲，否则当其从零状态转移时数据信号的上升沿或下降沿将太接近，从而确保任何信号 采样完成仅在数据信号的真零或基线状态期间发生，而不是在信号电平转换的任何周期期间发生。

公开(公告)号：US06173019B2

公开(公告)日：2001-01-09

申请号：US09076183

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: H04L2506

CPC classification number: H04L25/06 ,  H04L25/03885

Abstract: A closed feedback loop controls the baseline correction of a data signal. Detected signal information about the baseline and positive and negative peaks of the incoming data signal is processed to generate a baseline correction signal which identifies the difference, if any, between the present data signal baseline and that which is desired. This baseline correction signal is summed with the original data signal to bring its baseline into conformance with the desired baseline.

Abstract translation: 闭合反馈环路控制数据信号的基线校正。 处理关于输入数据信号的基线和正峰值和负峰值的检测信号信息，以产生基线校正信号，其识别当前数据信号基线与期望的基线之间的差异（如果有的话）。 该基线校正信号与原始数据信号相加，使其基线与期望的基线一致。

公开(公告)号：US6043766A

公开(公告)日：2000-03-28

申请号：US76187

申请日：1998-05-12

Applicant: Wong Hee ,  Abhijit Phanse

Inventor： Wong Hee ,  Abhijit Phanse

IPC: H03M1/12

CPC classification number: H03M1/12

Abstract: A distributive encoder for receiving and processing digital error signals representing variations in peak values of an equalized incoming digital data signal and in accordance therewith encoding error signals which represent signal peak errors in data signals for purposes of identifying erroneous signal baseline, peak and equalization conditions. The digital error signals represent variations in peak values of an equalized incoming digital data signal which includes a data signal baseline intermediate to its positive and negative peaks. Two sets of the digital error signals identify when present positive and negative levels transcend prior positive and negative levels, respectively, of the equalized incoming digital data signal. Using various subsets of these digital error signals, the distributive encoder generates encoded error signals which identify erroneous signal baseline, peak and equalization conditions. Using various ones of these encoded error signals, a baseline control circuit can generate a baseline control signal for use in controlling a correction of the equalized incoming digital data signal baseline, a peak control circuit can generate a peak control signal for use in controlling compensation for the positive and negative peaks of the equalized incoming digital data signal, and an equalization control circuit can generate a set of equalization control signals for use in controlling the equalization of the incoming digital data signal.

Abstract translation: 一种分配编码器，用于接收和处理表示均衡输入数字数据信号的峰值变化的数字误差信号，并根据编码误差信号，代表数据信号中的信号峰值误差，以识别错误的信号基线，峰值和均衡条件。 数字误差信号表示均衡输入数字数据信号的峰值的变化，其包括在其正峰值和负峰值之间的数据信号基线。 两组数字误差信号识别当存在正和负电平分别超过均衡输入数字数据信号的先前正和负电平时。 使用这些数字误差信号的各种子集，分布式编码器产生识别错误信号基线，峰值和均衡条件的编码误差信号。 使用这些编码的误差信号中的各种，基线控制电路可以产生用于控制均衡的输入数字数据信号基线的校正的基线控制信号，峰值控制电路可以产生用于控制补偿的峰值控制信号 均衡输入数字数据信号的正和负峰值以及均衡控制电路可以产生用于控制输入数字数据信号的均衡的一组均衡控制信号。