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公开(公告)号：US07088155B2
公开(公告)日：2006-08-08
申请号：US10500717
申请日：2002-01-16
Applicant: Akira Takahashi
Inventor： Akira Takahashi
IPC: H04L25/36
CPC classification number: H03L7/081 , H03L7/07 , H03L7/0814 , H03L7/087
Abstract: In a clock generation circuit generating a clock that is synchronized with a reference signal, it is an object to provide stable clocks by controlling phase jitter in a generated clock upon change of the reference signal, eliminate a stable-state phase difference between the reference signal and the generated clock so that control is eliminated, and allow the clock generation circuit to be integrated. The clock generation circuit is configured with multiple stages of PLL circuits such that PLL circuits 2 are provided for reference signals 1, respectively, and one of outputs from the PLL circuits 2 is selected to be fed to a PLL circuit 5 provided in a next stage. The phase fluctuation of a signal inputted to the PLL circuit 5 upon change of the reference signal 1 is reduced to control the phase jitter of the generated clock 6, thus allowing high loop gain in both the PLL circuit 2 and the PLL circuit 5. Then, phase difference between the reference signal 1 and the generated clock 6 is eliminated to eliminate control involved, so that the clock generation circuit may be integrated.
Abstract translation: 在产生与参考信号同步的时钟的时钟发生电路中，目的是通过在参考信号改变时控制生成的时钟中的相位抖动来提供稳定的时钟，消除参考信号之间的稳定状态相位差 和产生的时钟，从而消除了控制，并且允许时钟发生电路被集成。 时钟发生电路配置有多级PLL电路，使得分别为参考信号1提供PLL电路2，并且选择来自PLL电路2的输出中的一个被馈送到提供在下一级的PLL电路5 。 减少参考信号1改变后输入到PLL电路5的信号的相位波动，以控制所产生的时钟6的相位抖动，从而允许PLL电路2和PLL电路5中的高环路增益。 然后，消除参考信号1和产生的时钟6之间的相位差，以消除所涉及的控制，从而可以集成时钟产生电路。
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公开(公告)号：US5987084A
公开(公告)日：1999-11-16
申请号：US801573
申请日：1997-02-18
Applicant: Dominic Gerard Farmer
Inventor： Dominic Gerard Farmer
CPC classification number: G01S19/29 , H03D13/00 , H03L7/0994 , G01R25/00 , G01S19/37
Abstract: The output phase measures output by a digital phase lock loop (DPLL) are selectively modified to reduce instantaneous phase errors incurred whilst waiting until the DPLL locks before obtaining an accurate phase measurement of a signal. In one embodiment, the output phase of a low bandwidth DPLL is selectively modified when the input signal exhibits a significant dynamic transient by adding the error term generated by the DPLL phase detector to the output signal generated by the DPLL to generate a modified output signal used to perform phase measurements.
Abstract translation: 选择性地修改由数字锁相环（DPLL）输出的输出相位测量值，以减少在等待直到DPLL锁定之前产生的瞬时相位误差，然后才能获得信号的精确相位测量。 在一个实施例中，当输入信号通过将由DPLL相位检测器产生的误差项与由DPLL产生的输出信号相加而产生显着的动态瞬变时，选择性地修改低带宽DPLL的输出相位，以产生所使用的修改的输出信号 进行相位测量。
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3.发明授权Mechanism for automatically adjusting the phase of a transmission strobe clock signal to correct for misalignment of transmission clock and data signals 失效用于自动调整传输选通时钟信号的相位以校正传输时钟和数据信号的未对准的机制
公开(公告)号：US5870446A
公开(公告)日：1999-02-09
申请号：US653681
申请日：1996-03-11
Applicant: Dennis B. Mc Mahan , Mark D. Nevle , John M. Thorington, III , Dwight Edwin Wright
Inventor： Dennis B. Mc Mahan , Mark D. Nevle , John M. Thorington, III , Dwight Edwin Wright
CPC classification number: H04L7/0337 , H03L7/00 , H04L7/0091
Abstract: A transmission strobe clock signal control mechanism continuously monitors DTE data and transmission strobe clock signals used to strobe the DTE data onto a serial communication link, and automatically adjusts the phase of the transmission strobe clock signal in response to a misalignment between the two signals that exceeds acceptable limits. In a first embodiment, the DTE data signal is sampled by a high speed clock and clocked through a `data sample` shift register. Selected stages of the register, associated with a timing window that contains a transmission strobe clock signal edge, are coupled to an exclusive logic operation circuit, whose output indicates whether all of the data samples in the selected stages of the shift register are the same or not. If not, it is inferred that a data transition too close to the transmission strobe clock signal edge has occurred, necessitating an adjustment of the phase of the transmission strobe clock signal. In a second embodiment, a counter is clocked by high speed clock pulses between transitions in the transmission strobe clock signal and the data signal. A phase control circuit adjusts the phase of the transmission strobe clock signal in response to the number of high speed clock pulses counted not being between prescribed limits.
Abstract translation: 传输选通时钟信号控制机制连续地监视DTE数据和用于选通DTE数据到串行通信链路的传输选通时钟信号，并且响应于超过两个信号之间的未对准而自动调整传输选通时钟信号的相位 可接受的限度。 在第一实施例中，DTE数据信号由高速时钟采样并通过“数据采样”移位寄存器计时。 与包含传输选通时钟信号边沿的定时窗口相关联的寄存器的选定级耦合到专用逻辑运算电路，其输出指示移位寄存器的所选级中的所有数据采样是相同还是 不。 如果不是，则推断出发生了与传输选通时钟信号边沿太接近的数据转换，需要调整发送选通时钟信号的相位。 在第二实施例中，计数器由传输选通时钟信号和数据信号的转换之间的高速时钟脉冲计时。 相位控制电路响应于不在规定极限之间的高速时钟脉冲的数量来调整发送选通时钟信号的相位。
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公开(公告)号：US5815539A
公开(公告)日：1998-09-29
申请号：US679627
申请日：1996-07-12
Applicant: Gary R. Lennen
Inventor： Gary R. Lennen
CPC classification number: H04B1/7085 , G01S19/22 , G01S19/30 , H04B1/709 , G01S19/37
Abstract: A method and apparatus are disclosed for characterizing multipath-induced distortions in the autocorrelation function of a correlation receiver in order to reduce effects of these multipath-induced distortions on the accuracy of detecting the time of arrival of a received signal. The magnitude of the multipath-induced errors adversely affecting the shape of the autocorrelation function is estimated in real time, for example, through the use of secondary scanning correlators whose time base is independent of a typical receiver's detection-oriented correlators. This error is subtracted from the detection-oriented correlator's timing, thereby yielding a more accurate autocorrelation function.
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公开(公告)号：US5796795A
公开(公告)日：1998-08-18
申请号：US347618
申请日：1994-11-30
Applicant: Harry Edward Mussman , Hung-San Chen , Stephen P. Hartman
Inventor： Harry Edward Mussman , Hung-San Chen , Stephen P. Hartman
CPC classification number: H04J3/0685 , H04L7/0337
Abstract: A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations.
Abstract translation: 网络（10）包括宽带客户服务模块（B-CSM）（20）。 B-CSM（20）包括多个馈线接口卡（FIC）（36）和光线路卡（OLCS）（38），它们通过中平面组件（34）耦合在一起，使得每个FIC（36）耦合到 所有OLC（38）和每个OLC（38）通过连接器组（68）耦合到所有FIC（36）。 B-CSM（20）将许多OC-12 SONET馈线连接到许多OC-12 SONET线路。 在B-CSM（20）中，电路以STS-1速率进行电路切换。 以低于数据速率的频率振荡的参考时钟用有效载荷数据进行路由，使得其接收与由于处理而对有效载荷数据施加的延迟相似的延迟。 在第二级交换结构（50），其中需要从在B-CSM（20）内流动的信号中提取数据，时钟再生电路（32）产生以两倍数据速率振荡的主时钟信号，同步于延迟 参考时钟。 当时钟和数据被分散到从广泛分散的位置的点或小区域以及时钟和数据从点或小区域分布到广泛分散的位置时，几何补偿方案校正了定时偏移。
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Patent Agency Ranking6.发明授权Method for the reduction of phase noise introduced by the SDH network (Synchronous Digital Hierarchy Network) by pointer justification and integrated circuits for the implementation of the method 失效通过SDH网络（Synchronous Digital Hierarchy Network，同步数字体系网络）引入的降噪相关噪声的方法，通过指针调整和集成电路实现方法
公开(公告)号：US5774509A
公开(公告)日：1998-06-30
申请号：US247607
申请日：1994-05-23
Applicant: Silvano Frigerio , Stefano Gastaldello , Giovanni Russo
Inventor： Silvano Frigerio , Stefano Gastaldello , Giovanni Russo
CPC classification number: H03L7/0994 , H03L7/085 , H04J3/076
Abstract: A method and apparatus for reducing the phase noise introduced by pointer justification from a synchronous digital hierarchy network in a transmitted numerical signal. In the method and apparatus, occasional redundancies associated with bit justifications and fixed redundancies are combined with occasional prefiltered redundancies associated with the pointer justifications, and the combined signal is filtered in an analog phase locked loop. The occasional redundancies associated with the pointer justifications and at least part of the fixed redundancies with or without bit justifications are prefiltered in two stages, and the prefiltered signals are combined with the occasional redundancies associated with the bit justifications whenever these occasional redundancies are not prefiltered.
Abstract translation: 一种用于在发送的数字信号中从同步数字分层网络减少由指针对齐引入的相位噪声的方法和装置。 在方法和装置中，与位对称和固定冗余相关联的偶然冗余与与指针对齐相关联的偶尔预过滤冗余组合，并且组合信号在模拟锁相环中被滤波。 与指针对齐相关联的偶然冗余以及具有或不具有位对齐的固定冗余的至少一部分被预先过滤为两个阶段，并且将预过滤信号与偶数冗余相关联，并且每当这些偶然的冗余不被预先过滤时，与偶数冗余相关联。
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公开(公告)号：US5436943A
公开(公告)日：1995-07-25
申请号：US897647
申请日：1992-06-12
Applicant: Gary Borgen
Inventor： Gary Borgen
CPC classification number: G11B20/10527 , G11B20/22
Abstract: A digital audio signal processing circuit for eliminating the amplitude and phase components of logic induced modulation from a left right clock signal, a bit clock signal and digital data bits generated by a digital signal processor within a compact disk player. The digital audio signal processing circuit includes a trio of optical couplers for removing the amplitude component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits; a clock circuit for generating a system clock signal and a trio of D Flip-Flops for removing the phase component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits and a digital to analog converter for separating the data bits into left channel data bits and right channel data bits and for converting the left channel data bits into a first analog signal and the right channel data bits into a second analog signal for use by speakers or the like to provide stereo sound. An isolated power supply provides both analog and digital voltages to the electronic elements of digital audio signal processing circuit.
Abstract translation: 一种数字音频信号处理电路，用于消除来自左右时钟信号的逻辑感应调制的振幅和相位分量，位时钟信号和由光盘播放器内的数字信号处理器产生的数字数据位。 数字音频信号处理电路包括三个光耦合器，用于从左右时钟信号，位时钟信号和数字数据位中去除逻辑感应调制的振幅分量; 用于产生系统时钟信号的时钟电路和用于从左右时钟信号，位时钟信号和数字数据位除去逻辑感应调制的相位分量的D触发器三分之一和用于分离的数模转换器 将数据位转换为左声道数据位和右声道数据位，并将左声道数据位转换为第一模拟信号，将右声道数据位转换为第二模拟信号，供扬声器等使用以提供立体声。 隔离电源为数字音频信号处理电路的电子元件提供模拟和数字电压。
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公开(公告)号：US5414739A
公开(公告)日：1995-05-09
申请号：US974992
申请日：1992-11-12
Applicant: Naoya Kobayashi , Yoshitaka Takasaki , Sadao Mizokawa , Hisayuki Maruyama , Hiroshi Mabuchi , Eiichi Amada
Inventor： Naoya Kobayashi , Yoshitaka Takasaki , Sadao Mizokawa , Hisayuki Maruyama , Hiroshi Mabuchi , Eiichi Amada
Abstract: A transmission system which includes a plurality of reproduction nodes connected to each other in a cascade connection via a communication line. Each node includes a timing extraction circuit for extracting a timing signal from a signal received via the communication line, a discriminating circuit for converting the received signal into a digital signal according to the timing signal, and a processing circuit for processing, based on the timing signal, the digital signal outputted from the discriminating circuit and outputting the processed digital signal to the communication line. The timing extraction circuit includes a signal delay unit for supplying the timing signal with a signal delay time greater than a delay time occurring in the processing circuit.
Abstract translation: 一种传输系统，包括经由通信线路以级联方式彼此连接的多个再现节点。 每个节点包括定时提取电路，用于从经由通信线路接收的信号中提取定时信号;判别电路，用于根据定时信号将接收信号转换成数字信号;以及处理电路， 信号，从识别电路输出的数字信号并将经处理的数字信号输出到通信线路。 定时提取电路包括用于向定时信号提供大于在处理电路中出现的延迟时间的信号延迟时间的信号延迟单元。
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9.发明授权All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging 失效所有数字高速算法数据恢复方法和使用本地生成的补偿宽带时间标尺和数据边缘位置平均的装置
公开(公告)号：US5400370A
公开(公告)日：1995-03-21
申请号：US021924
申请日：1993-02-24
Applicant: Bin Guo
Inventor： Bin Guo
CPC classification number: H03L7/0814 , H04L7/0331 , H04L7/0337 , H04L7/0041
Abstract: An all digital data algorithmic recovery method and apparatus which operates at jitter greater than 25% and where run length is more than 1000 bits and which uses self calibrated delay elements to phase align a locally generated time ruler reference with the data average transition position to reliably establish the sampling time for retrieving data from an incoming binary sequence at the center of the data eye. The phase adjusted time ruler signal is used to sample transition positions of the data and the sampled data is statistically analyzed in a state machine wherein the time ruler is a broadband signal comprising a first and second base frequency and wherein the period of one of said frequencies is ##EQU1## where F.sub.R equals the receiver local clock frequency and F.sub.T equals the frequency of the distant clock.
Abstract translation: 全数字数据算法恢复方法和装置，其抖动大于25％，运行长度大于1000位，并且使用自校准的延迟元件将本地生成的时间标尺参考与数据平均转换位置相位对准 建立从数据眼中心的输入二进制序列检索数据的采样时间。 相位调整时间标尺信号用于对数据的转换位置进行采样，并且采样数据在状态机中进行统计分析，其中时间标尺是包括第一和第二基本频率的宽带信号，并且其中所述频率之一的周期 是
，其中FR等于接收机本地时钟频率，FT等于远距离时钟的频率。 -
公开(公告)号：US5317600A
公开(公告)日：1994-05-31
申请号：US882452
申请日：1992-05-12
Applicant: Antti Kansakoski
Inventor： Antti Kansakoski
CPC classification number: H04L7/0062
Abstract: The channel frequency of a digital radiotelephone is coarse tuned utilizing the phase information of the symbols. According to the invention the phase change between the measured phases of one or more received symbols (d) and the previous symbol (e) is detected, the phase change being compared with allowed phase changes. Based on this a decision (g) is made concerning the phase of the transmitted symbol, the phase error (f.sub.err) or difference between the decision (g) and the measured phase change (d) is generated, and on this basis the channel frequency is adjusted.
Abstract translation: 使用符号的相位信息来粗调数字无线电话机的信道频率。 根据本发明，检测一个或多个接收符号（d）和先前符号（e）的测量相位之间的相位变化，将相变与允许的相位变化进行比较。 基于此，关于发送符号的相位做出决定（g），产生相位误差（ferr）或判决（g）与测量的相位变化（d）之间的差异，并且在此基础上，信道频率 被调整。
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