公开(公告)号：US20240032291A1

公开(公告)日：2024-01-25

申请号：US17888424

申请日：2022-08-15

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H01L27/11524 ,  H01L27/11558 ,  H01L29/66

CPC classification number: H01L27/11524 ,  H01L27/11558 ,  H01L29/66825

Abstract: A non-volatile memory and fabrication method thereof are disclosed. The non-volatile memory includes at least one 2T memory cell. Each 2T memory cell includes a semiconductor substrate, a first stacked gate and a second stacked gate formed on the semiconductor substrate, and a drain region, a common source/drain region and a source region formed in the semiconductor substrate. The source region and the common source/drain region are both N-type doped, and the drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The 2T memory cell is capable of preventing erroneous data determination caused by over erase and has both a low programming current and a high reading current, which improves the performance of the non-volatile memory.

公开(公告)号：US20240405015A1

公开(公告)日：2024-12-05

申请号：US18336707

申请日：2023-06-16

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H01L27/02 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device with ESD protection structure and a method of making it are disclosed. The semiconductor device with ESD protection structure includes at least one gate and source and drain regions on opposite sides of the at least one gate that constitute at least a discharging MOSFET. The gate includes first gate portions having a first dopant concentration and a second gate portion having a second dopant concentration. The first dopant concentration is lower than the second dopant concentration. The at least one first gate portions are lower portions of the gate above the edges of an active area, and the second gate portion is the remaining portion of the at least one gate other than the first gate portions.

公开(公告)号：US20240306363A1

公开(公告)日：2024-09-12

申请号：US18127321

申请日：2023-03-28

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H10B12/00

CPC classification number: H10B12/033 ,  H10B12/315

Abstract: A multilayer capacitor, a method for making the multilayer capacitor, and a memory device are disclosed by the present invention. The multilayer capacitor made by the method is connected to a capacitor terminal and includes a multilayer fin structure including horizontal and vertical fin elements. A first conductive layer covers a surface of the multilayer fin structure and thereby has a large surface area. A capacitor dielectric layer covers a surface of the first conductive layer, and a second conductive layer covers the capacitor dielectric layer. In this way, the multilayer capacitor has desirably large capacitance. In addition, in the method, after a layer stack is formed, it is processed into the multilayer fin structure by self-aligned anisotropic and isotropic etch, which do not require the use of any photomask or the deposition of any additional layer, resulting in low manufacturing cost. The memory device includes the multilayer capacitor.

公开(公告)号：US20240032290A1

公开(公告)日：2024-01-25

申请号：US17888430

申请日：2022-08-15

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H01L27/11521 ,  H01L27/11556

CPC classification number: H01L27/11521 ,  H01L27/11556

Abstract: A split-gate non-volatile memory, fabrication and control methods thereof are disclosed by the present application. The split-gate non-volatile memory includes at least one memory cell. Each memory cell includes: a drain region and an N-type doped source region, both formed in the semiconductor substrate; and a stacked gate, first spacers, a select gate and second spacers, all formed between the N-type doped source region and the drain region. The drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The memory cell is advantageous in the prevention of erroneous data determination caused by over-erase, a low programming current and a high reading current. Further, the split-gate structure will not lead to a significant increase in the memory cell's area, enhancing overall performance of the split-gate non-volatile memory.

公开(公告)号：US20240179896A1

公开(公告)日：2024-05-30

申请号：US18089063

申请日：2022-12-27

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H10B20/25 ,  G11C17/18

CPC classification number: H10B20/25 ,  G11C17/18

Abstract: A 1.5T one-time programmable memory device and a method for fabricating it re disclosed. The 1.5T OTP memory device includes at least one 1.5T memory cell formed in an active area of a semiconductor substrate. The 1.5T memory cell includes one select transistor and one half of a grounding transistor. This structure is simple. Moreover, in the grounding transistor, a portion of a thin gate dielectric layer is sandwiched between a doped junction region coupled to a source region in the select transistor and a grounding gate. During programming of the 1.5T memory cell, a voltage on the drain region in the select transistor can be coupled to the doped junction region to cause the thin gate dielectric layer portion sandwiched between the doped junction region and the grounding gate to rupture at a low programming voltage.

公开(公告)号：US20240087660A1

公开(公告)日：2024-03-14

申请号：US17953717

申请日：2022-09-27

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: G11C17/12 ,  H10B20/25

CPC classification number: G11C17/12 ,  H10B20/25

Abstract: The present invention relates to an OTP memory device, a method for operating the OTP memory device and a method for fabricating the OTP memory device. In the OTP memory device, a PN junction is formed between a source-side LDD region and a source region in each OTP memory cell. During programming of the OTP memory cell, the PN junction is broken down, providing one-time programmability. Moreover, its circuit layout is simple, helping to achieve a reduced chip area and lower cost. In the method for fabricating the OTP memory device, OTP memory cells in the OTP memory device and MOS transistors are simultaneously formed on surface regions of a semiconductor substrate, reducing fabrication complexity and cost of the OTP memory device and making it suitable for mass production.