公开(公告)号：US20170200502A1

公开(公告)日：2017-07-13

申请号：US15398014

申请日：2017-01-04

申请人： HYUN JUN YOON ,  JI-SANG LEE

发明人： HYUN JUN YOON ,  JI-SANG LEE

IPC分类号： G11C16/08 ,  G11C16/20 ,  G11C16/26

CPC分类号： G11C16/08 ,  G11C16/20 ,  G11C16/26 ,  G11C16/32

摘要： A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

公开(公告)号：US20170011799A1

公开(公告)日：2017-01-12

申请号：US14996249

申请日：2016-01-15

申请人： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

发明人： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

摘要翻译： 非易失性存储器包括存储单元阵列，行解码器电路和页缓冲电路。 行解码器电路响应于从外部设备接收到的写入命令，在第一预充电操作时，对连接到所选存储块的串选择晶体管的串选择线施加导通电压。 页缓冲器电路响应于写入命令，在第一预充电操作下，连接到串选择晶体管的第一电压至位线，而不管加载数据如何，并施加第一电压和 基于所加载的数据，在第二预充电操作中通过第二预充电电路对位线施加第二电压。 在第一预充电操作期间，写数据被加载到页缓冲电路。

公开(公告)号：US20130064013A1

公开(公告)日：2013-03-14

申请号：US13528886

申请日：2012-06-21

申请人： JI-SANG LEE ,  KI HWAN CHOI

发明人： JI-SANG LEE ,  KI HWAN CHOI

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3418

摘要： A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from the first word line using a different voltage according to a state of the data read from the second word line. The number of read voltages used to distinguish an erased state and a first programmed state is greater than the number of read voltages used to distinguish a second programmed state and a third programmed state.

摘要翻译： 提供非易失性存储器件，其数据读取方法和记录介质。 该方法包括接收存储单元阵列中的第一字线的数据读取命令，从与第一字线相邻的第二字线读取数据，以及根据第一字线的状态从第一字线读取数据，使用不同的电压 从第二个字线读取数据。 用于区分擦除状态和第一编程状态的读取电压的数量大于用于区分第二编程状态和第三编程状态的读取电压的数量。

公开(公告)号：US20160071581A1

公开(公告)日：2016-03-10

申请号：US14674005

申请日：2015-03-31

申请人： JI-SANG LEE

发明人： JI-SANG LEE

IPC分类号： G11C11/56

CPC分类号： G11C11/5671 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a program operation a plurality of memory cells are programmed depending on data stored in first and second data latches. Verification read operations are performed for the plurality of memory cells using different verification voltages respectively corresponding to different program states and collecting verification read results of the verification read operations. The first data latches and the second data latches are updated depending on the collected verification read results.

摘要翻译： 在程序操作中，根据存储在第一和第二数据锁存器中的数据对多个存储器单元进行编程。 使用分别对应于不同程序状态的不同验证电压并且收集验证读取操作的验证读取结果，对多个存储器单元执行验证读取操作。 根据收集的验证读取结果，第一个数据锁存器和第二个数据锁存器被更新。

公开(公告)号：US20170125128A1

公开(公告)日：2017-05-04

申请号：US15207774

申请日：2016-07-12

申请人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

发明人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

IPC分类号： G11C29/56 ,  G11C8/10 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C29/1201 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12 ,  G11C7/14 ,  G11C7/222 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C27/02 ,  G11C29/42 ,  G11C29/50012 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411 ,  G11C2029/5004 ,  G11C2211/5642

摘要： A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≦N, L>1, P≦M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.