公开(公告)号：US5998251A

公开(公告)日：1999-12-07

申请号：US975492

申请日：1997-11-21

申请人： H. J. Wu ,  Shih-Wei Sun ,  Jacob Chen ,  Tri-Rung Yew

发明人： H. J. Wu ,  Shih-Wei Sun ,  Jacob Chen ,  Tri-Rung Yew

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that become bit line contacts and logic interconnects. A layer of tungsten is deposited and patterned to provide upper capacitor electrodes and to complete the bit line contacts and logic interconnects. This first level tungsten layer also can provide bit line wiring. The 1/2 V.sub.cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring also used by the logic circuits.

摘要翻译： 使用避免嵌入式DRAM集成的一些最重要的处理挑战的过程来提供具有逻辑电路阵列和嵌入式DRAM电路阵列的集成电路器件。 为嵌入式DRAM电路提供转移FET和布线，并且在该过程的初始阶段为器件的逻辑部分提供FET。 逻辑FET的栅极电极和源极/漏极区域在该初始阶段经受自对准硅化物处理，并且在嵌入式DRAM区域和逻辑电路区域上均设置厚平坦化的氧化物层。 接下来使用常规蚀刻，氮化钛沉积和钨沉积步骤形成电容器和逻辑互连。 形成接触通孔以暴露DRAM传输FET的每个源极漏极区域并暴露在逻辑电路内的选择导体。 氮化钛层通过平坦化的氧化物层沉积在器件上并在各种接触孔内。 在器件上提供电容器介电层，然后至少选择性地从形成位线接触和逻辑互连的接触孔中去除电容器介质层。 沉积钨层并图案化以提供上层电容器电极并完成位线接触和逻辑互连。 该第一级钨层也可以提供位线布线。 上电容器电极的+ E，fra 1/2 + EE Vcc电位可以使用也由逻辑电路使用的互连布线的电平提供给电路。

公开(公告)号：US06238972B1

公开(公告)日：2001-05-29

申请号：US09096351

申请日：1998-06-12

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L28/84

摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.

摘要翻译： 通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si） 的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。 在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新沉积以在电极的表面上提供第二层HSG-Si。 如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。 在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。 在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。 该纹理硅结构形成DRAM电容器的下电极。

公开(公告)号：US07378740B2

公开(公告)日：2008-05-27

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US6020258A

公开(公告)日：2000-02-01

申请号：US982266

申请日：1997-12-01

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76834 ,  Y10S438/97

摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.

摘要翻译： 形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。 在层间电介质的表面上设置一级布线。 第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。 金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。 去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。

公开(公告)号：US5960299A

公开(公告)日：1999-09-28

申请号：US181466

申请日：1998-10-28

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  Y10S148/05

摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.

摘要翻译： 提供了一种用于在集成电路中制造浅沟槽隔离（STI）结构的半导体制造方法，其可以防止在STI结构的氧化物塞中发生微细纹理，从而进一步防止桥接效应的发生， 要通过STI结构电隔离的电路元件之间的电路。 该方法的特征在于使用激光退火工艺来除去在用于去除氧化物层的上部以形成氧化物的化学机械抛光（CMP）工艺期间在氧化物塞的顶表面上形成的微观尺度 堵塞该方法因此可以防止桥接效应的发生和由于形成在现有技术中将会出现的微纹理造成的短路。

公开(公告)号：US06114200A

公开(公告)日：2000-09-05

申请号：US996697

申请日：1997-12-23

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/60

摘要： A method of fabricating a DRAM device to reduce the stress and enhance the adhesion between the top electrode and the interlevel dielectric layer, includes forming a titanium layer between the top electrode and the interlevel dielectric layer. A titanium oxide layer and a titanium silicide are formed between the titanium layer and the interlevel dielectric layer in post thermal procedures, which enhances the adhesion and avoids cracks and leakage current between the top electrode and the interlevel dielectric layer.

摘要翻译： 一种制造DRAM器件以减少应力并增强顶部电极和层间电介质层之间的粘附性的方法包括在顶部电极和层间电介质层之间形成钛层。 在后热工程中，在钛层和层间电介质层之间形成氧化钛层和硅化钛，这增强了附着力，避免了顶部电极和层间电介质层之间的裂纹和漏电流。

公开(公告)号：US6025264A

公开(公告)日：2000-02-15

申请号：US52608

申请日：1998-03-31

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Yimin Huang

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Yimin Huang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

摘要翻译： 一种用于形成阻挡层的方法，包括以下步骤：首先提供其上已经形成有导电层的半导体衬底。 然后，在导电层和半导体衬底上沉积诸如有机低k电介质层的电介质层。 接下来，形成在暴露导电层的电介质层中的开口。 此后，第一阻挡层沉积到开口和周围区域中。 第一阻挡层可以是通过等离子体增强化学气相沉积（PECVD）法，低压化学气相沉积法（LPCVD）法，电子束 蒸发法或溅射法。 最后，在第一阻挡层上形成第二阻挡层。 第二阻挡层可以是钛/氮化钛（Ti / TiN）层，氮化钨（WN）层，钽（Ta）层或氮化钽（TaN）层。

公开(公告)号：US6013555A

公开(公告)日：2000-01-11

申请号：US807960

申请日：1997-02-28

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Chung-Shien Kao, deceased

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Chung-Shien Kao, deceased

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/1085 ,  H01L28/84 ,  Y10S438/964

摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and depositing a layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. A thin layer of amorphous silicon is then formed over the HSG-Si layer. This textured polysilicon structure forms the lower electrode of the DRAM capacitor. A dielectric layer is formed on the lower electrode, and an upper electrode is formed from a second layer of doped polysilicon. As-formed HSG-Si grains tend to form sharp intersections with the polysilicon layers on which they grow. When these HSG-Si grains are exposed to a thermal oxidation environment, poor quality oxides are formed at the sharp corners between the HSG-Si grains and the doped polysilicon layer. The poor quality oxides at the sharp corners between the HSG-Si grains and the doped polysilicon layer break down comparatively readily, and appears to cause leakage currents in capacitors having HSG-Si electrodes. By growing a thin amorphous silicon layer over the surface of the HSG-Si layer, the intersection between the HSG-Si grains and the layer of polysilicon is rounded. Subsequent growth of a thermal oxide, or the formation of other dielectric layers, provides a more reliable capacitor.

摘要翻译： DRAM单元的电容器通过沉积掺杂多晶硅层形成，图案化掺杂多晶硅层以限定电容器的下电极的范围，并在掺杂的层上沉积半球晶硅（HSG-Si）层 多晶硅 然后在HSG-Si层上形成薄层的非晶硅。 该纹理多晶硅结构形成DRAM电容器的下电极。 电介质层形成在下电极上，上电极由第二掺杂多晶硅层形成。 形成的HSG-Si晶粒倾向于与它们生长的多晶硅层形成锐利的交叉。 当这些HSG-Si晶粒暴露于热氧化环境时，在HSG-Si晶粒和掺杂多晶硅层之间的尖角处形成质量差的氧化物。 在HSG-Si晶粒和掺杂多晶硅层之间的尖角处的质量差的氧化物相对容易地分解，似乎在具有HSG-Si电极的电容器中引起漏电流。 通过在HSG-Si层的表面上生长薄的非晶硅层，HSG-Si晶粒和多晶硅层之间的交点是圆形的。 随后的热氧化物生长或其它介电层的形成提供了更可靠的电容器。

公开(公告)号：US6010931A

公开(公告)日：2000-01-04

申请号：US864299

申请日：1997-05-28

申请人： Shih-Wei Sun ,  Tri-Rung Yew

发明人： Shih-Wei Sun ,  Tri-Rung Yew

IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10852

摘要： A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.

摘要翻译： 形成DRAM的方法包括在衬底上形成转移FET，所述FET在衬底上方的栅极氧化物层上具有栅极，并且在栅极之下的沟道区域的任一侧上的衬底中的第一和第二源极/漏极区域 。 第一和第二源极/漏极区域通常在间隔物蚀刻工艺中暴露或接近露出。 在整个结构上沉积氮化硅蚀刻停止层，然后在器件上沉积厚层氧化物。 进行化学机械抛光以在厚氧化物层上提供平坦表面。 在第一源极/漏极区域上方的厚的氧化物层形成开口，在蚀刻停止层处停止。 蚀刻停止层在氧化物的厚层的开口内去除，并且下面的薄氧化物层被蚀刻。 然后可以形成与第一源极/漏极区域的暴露部分接触的电容器电极。 可以使用类似的自对准方法来形成使用蚀刻停止层作为位线接触蚀刻停止的器件的位线接触。 该方法的实践提供了具有改进的可靠性和易用性的制造方法，特别是当实施用于包含高介电常数电介质的DRAM电容器时。 优选用于这种DRAM电容器的材料具有较小的工艺裕度，因此特别受益于改进的结构和工艺。

公开(公告)号：US5801094A

公开(公告)日：1998-09-01

申请号：US873500

申请日：1997-06-12

申请人： Tri-Rung Yew ,  Meng-Chang Liu ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Meng-Chang Liu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/7681 ,  H01L21/76804

摘要： A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.

摘要翻译： 双镶嵌工艺通过首先在器件结构上提供层间氧化物并用蚀刻停止层覆盖层间氧化物层，形成两层金属互连结构。 蚀刻停止层被图案化以形成对应于将要形成在两层互连结构的第一层中的互连图案的开口。 在蚀刻停止层被图案化之后，在蚀刻停止层上方提供金属间氧化物层。 因为蚀刻停止层相对较薄，所以形成在金属间氧化物层的表面上的形貌相对较小。 然后在金属间氧化物层之上提供光致抗蚀剂掩模，其中掩模中的开口在布线的图案中的金属间氧化物层的暴露部分中设置有互连结构的第二层。 蚀刻金属间氧化物层，并且蚀刻工艺继续在层间氧化物中形成开口，其中层间氧化物被蚀刻停止层中的开口暴露。 因此，在单个蚀刻步骤中，限定了用于二级布线和第一级互连的开口。 然后将金属沉积在结构上，通过化学机械抛光除去多余的金属以限定两层互连结构。