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    FINFET WITH HIGH-K SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
    1.
    发明申请
    FINFET WITH HIGH-K SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER 审中-公开

    公开(公告)号：US20190259619A1

    公开(公告)日：2019-08-22

    申请号：US15902098

    申请日：2018-02-22

    申请人： GLOBALFOUNDRIES INC.

    发明人： Hui Zang ,  Guowei Xu ,  Keith Tabakman

    IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

    摘要： In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

    FinFET with high-k spacer and self-aligned contact capping layer
    2.
    发明授权
    FinFET with high-k spacer and self-aligned contact capping layer 有权

    公开(公告)号：US10734233B2

    公开(公告)日：2020-08-04

    申请号：US15902098

    申请日：2018-02-22

    申请人： GLOBALFOUNDRIES INC.

    发明人： Hui Zang ,  Guowei Xu ,  Keith Tabakman

    IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

    摘要： In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

    METHODS OF FORMING A GATE STRUCTURE-TO-SOURCE/DRAIN CONDUCTIVE CONTACT AND THE RESULTING DEVICES
    3.
    发明申请
    METHODS OF FORMING A GATE STRUCTURE-TO-SOURCE/DRAIN CONDUCTIVE CONTACT AND THE RESULTING DEVICES 审中-公开

    公开(公告)号：US20190043758A1

    公开(公告)日：2019-02-07

    申请号：US15670366

    申请日：2017-08-07

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Keith Tabakman ,  Ruilong Xie

    IPC分类号： H01L21/8234 ,  H01L21/311 ,  H01L21/283 ,  H01L21/768

    摘要： Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.

    Methods of forming a gate structure-to-source/drain conductive contact and the resulting devices
    8.
    发明授权
    Methods of forming a gate structure-to-source/drain conductive contact and the resulting devices 有权

    公开(公告)号：US10297504B2

    公开(公告)日：2019-05-21

    申请号：US15670366

    申请日：2017-08-07

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Keith Tabakman ,  Ruilong Xie

    IPC分类号： H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234

    摘要： Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.