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    ELECTRODEPOSITION SYSTEMS AND METHODS THAT MINIMIZE ANODE AND/OR PLATING SOLUTION DEGRADATION
    4.
    发明申请
    ELECTRODEPOSITION SYSTEMS AND METHODS THAT MINIMIZE ANODE AND/OR PLATING SOLUTION DEGRADATION 审中-公开

    公开(公告)号：US20170211199A1

    公开(公告)日：2017-07-27

    申请号：US15482938

    申请日：2017-04-10

    Applicant: GlobalFoundries Inc.

    Inventor： Charles L. Arvin ,  Harry D. Cox ,  Eric D. Perfecto

    IPC: C25D5/18 ,  C25D17/10 ,  C25D21/12

    CPC classification number: C25D5/18 ,  C25D17/10 ,  C25D21/12

    Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e., when the first electrode is removed from the plating solution), wherein the second electrode and the third electrode have opposite polarities that switch at regular, relatively fast, intervals, thereby limiting degradation of the second electrode and/or the plating solution.

    Passivation layer topography
    6.
    发明授权
    Passivation layer topography 有权
    钝化层地形

    公开(公告)号：US09466547B1

    公开(公告)日：2016-10-11

    申请号：US14734600

    申请日：2015-06-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

    IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/54

    CPC classification number: H01L23/3171 ,  H01L21/4853 ,  H01L21/563 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/03

    Abstract: A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

    Abstract translation: 在集成电路（IC）芯片钝化层内形成一种形貌结构。 形貌结构包括在钝化层的顶表面下方延伸的沟槽，并且在与IC芯片的最上面布线相关联的钝化层下面的最上面的金属间介电层的顶表面之上。 形貌结构还可以包括沿着沟槽的周边的钝化层的顶表面上方的脊。 形状结构可以位于一系列IC芯片接触焊盘之间和/或可以位于特定的IC芯片接触焊盘周围。 形貌结构增加了钝化层的表面积，从而增加了与钝化层的底部填充结合。 地形结构还影响毛细管底部填充物的毛细管运动，并且可以定位成加速，减慢或转移毛细管底部填充物的移动。

    Electrodeposition systems and methods that minimize anode and/or plating solution degradation
    7.
    发明授权
    Electrodeposition systems and methods that minimize anode and/or plating solution degradation 有权

    公开(公告)号：US10041183B2

    公开(公告)日：2018-08-07

    申请号：US15482938

    申请日：2017-04-10

    Applicant: GlobalFoundries Inc.

    Inventor： Charles L. Arvin ,  Harry D. Cox ,  Eric D. Perfecto

    IPC: C25D21/12 ,  C25D5/18 ,  C25D17/10

    Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e., when the first electrode is removed from the plating solution), wherein the second electrode and the third electrode have opposite polarities that switch at regular, relatively fast, intervals, thereby limiting degradation of the second electrode and/or the plating solution.

    Photonics chip
    8.
    发明授权
    Photonics chip 有权

    公开(公告)号：US10409006B2

    公开(公告)日：2019-09-10

    申请号：US15874210

    申请日：2018-01-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeffrey P. Gambino ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Charles L. Arvin ,  Robert Leidy

    IPC: G02B6/12 ,  G02B6/34 ,  G02B6/30 ,  G02B6/124 ,  G02B6/13 ,  G02B6/36

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

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