公开(公告)号：US09805930B2

公开(公告)日：2017-10-31

申请号：US15196035

申请日：2016-06-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryo Tanaka ,  Shinya Takashima ,  Katsunori Ueno ,  Masaharu Edo

IPC: H01L21/00 ,  H01L21/18 ,  H01L21/02

CPC classification number: H01L21/187 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02694 ,  H01L29/66204 ,  H01L29/8611

Abstract: A method of manufacturing a nitride semiconductor device is provided, comprising: forming, on a substrate, a first laminated body where a first nitride semiconductor layer, a second nitride semiconductor layer and a third nitride semiconductor layer are laminated in this order; subsequent to the forming, removing a partial region of the third nitride semiconductor layer, subsequent to the removing; implanting ions to the first nitride semiconductor layer from the partial region where the third nitride semiconductor layer is removed at least through the second nitride semiconductor layer; and subsequent to the implanting the ions, annealing the first laminated body.

公开(公告)号：US11257676B2

公开(公告)日：2022-02-22

申请号：US16021036

申请日：2018-06-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hideaki Matsuyama ,  Shinya Takashima ,  Katsunori Ueno ,  Ryo Tanaka ,  Masaharu Edo ,  Daisuke Mori ,  Hirotaka Suda ,  Hideaki Teranishi ,  Chizuru Inoue

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/24 ,  H01L29/267 ,  H01L29/20 ,  H01L29/08 ,  H01L29/207 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225

Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

公开(公告)号：US11062907B2

公开(公告)日：2021-07-13

申请号：US16299142

申请日：2019-03-12

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Shinya Takashima ,  Ryo Tanaka ,  Yuta Fukushima ,  Hideaki Teranishi

IPC: H01L21/265 ,  H01L29/06 ,  H01L29/20 ,  H01L29/207 ,  H01L29/32 ,  H01L29/78 ,  H01L21/02 ,  H01L29/861 ,  H01L21/266

Abstract: A nitride semiconductor device is provide, the nitride semiconductor device including: an epitaxial layer; and an ion implantation layer that is provided on the epitaxial layer over a continuous depth range that extends over 100 nm or longer, and has a P type doping concentration equal to or higher than 1×1017 cm−3, wherein the ion implantation layer has a region with a crystal defect density equal to or lower than 1×1016 cm−3, the region being located in a range which is on an upper-surface-side of an interface between the epitaxial layer and the ion implantation layer, and is within 100 nm from the interface.

公开(公告)号：US09754783B2

公开(公告)日：2017-09-05

申请号：US14848214

申请日：2015-09-08

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Shinya Takashima ,  Ryo Tanaka ,  Katsunori Ueno ,  Masaharu Edo

IPC: H01L21/02 ,  H01L21/18 ,  H01L21/22 ,  C23C16/56 ,  H01L29/20 ,  C30B23/02 ,  C23C16/30 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  C30B25/02 ,  C30B29/40

CPC classification number: H01L21/0254 ,  C23C16/303 ,  C23C16/56 ,  C30B23/02 ,  C30B25/02 ,  C30B29/406 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/18 ,  H01L21/22 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7827

Abstract: A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming an aluminum nitride layer on a surface of the nitride-based semiconductor layer at a forming temperature and in a growth atmosphere for aluminum nitride; and performing a thermal treatment on the nitride-based semiconductor layer and the aluminum nitride layer, at a treatment temperature that is higher than the forming temperature and in the growth atmosphere for aluminum nitride. For example, an n-GaN layer is formed on an n-GaN substrate, and thereafter the n-GaN layer is doped with an impurity. A cap layer of an epitaxial film made up of AlN is formed, by MOCVD, on the surface of the n-GaN layer. Thermal treatment for activation annealing activates the impurity in the n-GaN layer in an atmosphere that causes AlN to grow, or in an atmosphere in which growth and decomposition of AlN are substantially balanced.

公开(公告)号：US12237379B2

公开(公告)日：2025-02-25

申请号：US17584043

申请日：2022-01-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryo Tanaka ,  Yuki Ohuchi ,  Katsunori Ueno ,  Shinya Takashima

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

Abstract: A method for manufacturing a nitride semiconductor device including: forming an N-type region in a nitride semiconductor layer; implanting ions of an acceptor element into a region under the N-type region in the nitride semiconductor layer; and forming a first P-type region under the N-type region by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type region includes implanting ions of a donor element into the nitride semiconductor layer such that concentration of the donor element in the N-type region is equal to or greater than concentration of the acceptor element in the first P-type region. The implanting ions of the acceptor element into a region under the N-type region includes implanting ions of the acceptor element such that concentration of the acceptor element in the first P-type region is 1×1019 cm−3 or more and 1×1021 cm−3 or less.

公开(公告)号：US11862687B2

公开(公告)日：2024-01-02

申请号：US17001617

申请日：2020-08-24

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryo Tanaka ,  Shinya Takashima ,  Hideaki Matsuyama ,  Katsunori Ueno ,  Masaharu Edo

IPC: H01L29/20 ,  H01L21/20 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/2003 ,  H01L21/20 ,  H01L21/265 ,  H01L29/0684 ,  H01L29/16 ,  H01L29/66734 ,  H01L29/7802

Abstract: A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.

公开(公告)号：US11862686B2

公开(公告)日：2024-01-02

申请号：US16919560

申请日：2020-07-02

Applicant: Fuji Electric Co., Ltd.

Inventor： Shinya Takashima ,  Ryo Tanaka ,  Katsunori Ueno

IPC: H01L29/78 ,  H01L29/20 ,  H01L21/02 ,  H01L21/324 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L21/02175 ,  H01L21/2253 ,  H01L21/3245 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a nitride semiconductor device includes: selectively ion-implanting an element that is other than p-type impurities and n-type impurities into a first region in a first primary surface of a gallium nitride layer so as to generate crystal defects in the first region; selectively ion-implanting a p-type impurity into a second region in the gallium nitride layer, the second region being shallower than the first region in a depth direction and being within the first region in a plan view; and thermally treating said gallium nitride layer that has been ion-implanted with said element and said p-type impurity so as to thermally diffuse said p-type impurity in the second region into a third region that is within the first region and that surrounds a bottom and sides of the second region.