公开(公告)号：US20230420549A1

公开(公告)日：2023-12-28

申请号：US18138956

申请日：2023-04-25

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hong-fei LU

IPC分类号： H01L29/739 ,  H01L29/423 ,  H01L29/36 ,  H01L29/08

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H01L29/36 ,  H01L29/0804

摘要： IGBT includes an n-type drift layer, an n-type accumulation layer provided on the upper surface of the drift layer having higher impurity concentration than the drift layer, a base layer provided on the upper surface of the accumulation layer, a gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer through a gate insulating film, and a dummy electrode embedded inside a dummy trench provided to face the gate trench across the base layer and the accumulation layer through a dummy insulating film. The base layer has a p-type active base region and a p-type floating base region arranged alternately in the extending direction of the gate trench, and an n-type base isolation region isolating the active base region and the floating base region.

公开(公告)号：US20150060938A1

公开(公告)日：2015-03-05

申请号：US14536980

申请日：2014-11-10

申请人： Fuji Electric Co., Ltd.

发明人： Hong-fei LU

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/304 ,  H01L29/06 ,  H01L29/36

CPC分类号： H01L29/7395 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/404 ,  H01L29/66333

摘要： An n− type drift region, an n-type field stop region, and an n− type FZ wafer are provided in an n− type wafer. An edge termination structure portion is provided in a chip outer peripheral portion of regions of the n− type wafer, surrounding an active region inside a chip inner portion. A thickness of the chip inner portion is less than a thickness of the chip outer peripheral portion owing to a groove. A p-type collector region is in contact with the n− type FZ wafer and n-type field stop region. A collector electrode is in contact with the p-type collector region. A second distance between the collector electrode and the n-type field stop region in the edge termination structure portion is greater than a first distance between the collector electrode and the n-type field stop region in the active region.

摘要翻译： 在n型晶片中设置n型漂移区，n型场停止区和n型FZ晶片。 边缘终端结构部分设置在n型晶片的区域的芯片外周部分中，围绕芯片内部部分内的有源区域。 由于凹槽，芯片内部的厚度小于芯片外周部的厚度。 p型集电极区域与n型FZ晶片和n型场停止区域接触。 集电极与p型集电极区域接触。 在边缘终端结构部分中的集电极和n型场阻挡区之间的第二距离大于有源区中集电极与n型场停止区之间的第一距离。

公开(公告)号：US20130221403A1

公开(公告)日：2013-08-29

申请号：US13859423

申请日：2013-04-09

申请人： Fuji Electric Co., Ltd.

发明人： Hong-fei LU

IPC分类号： H01L29/78 ,  H01L29/739

CPC分类号： H01L29/7827 ,  H01L21/761 ,  H01L21/76251 ,  H01L21/84 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/32 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

摘要： A semiconductor device and related method of manufacturing a semiconductor device that has an active region in the inner circumference of a chip with a thickness less than that of the outer circumference of the chip in which a termination structure is provided. An n field stop region, a p collector region, and a collector electrode are on the other main surface of an n− drift region. The n field stop region, the p collector region, and the collector electrode extend from the active region to the termination structure. In the termination structure, a silicon oxide film has a position from a first main surface of the n− drift region in a first depth direction substantially the same as the position of the collector electrode from the first main surface of the n− drift region (2) in the first depth direction in the active region.

摘要翻译： 一种制造半导体器件的半导体器件及其相关方法，该半导体器件在芯片的内周中具有比设置有端接结构的芯片的外周的厚度小的有源区。 n个场停止区域，p集电极区域和集电极电极在n漂移区域的另一个主表面上。 n场停止区域，p集电极区域和集电极电极从有源区域延伸到终端结构。 在端接结构中，氧化硅膜具有从与n-漂移区域的第一主表面的集电极的位置大致相同的第一深度方向上的n-漂移区域的第一主表面的位置（ 2）在有源区域中的第一深度方向上。

公开(公告)号：US20240079481A1

公开(公告)日：2024-03-07

申请号：US18357158

申请日：2023-07-24

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hong-fei LU

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/861

CPC分类号： H01L29/7397 ,  H01L29/1095 ,  H01L29/861

摘要： Provided is a semiconductor device including: a plurality of trench portions which are provided to positions below a base region from an upper surface of a semiconductor substrate and are arranged next to one another in a first direction on the upper surface of the semiconductor substrate; a first lower end region of a second conductivity type, which is arranged at a first depth position and is provided in contact with a lower end of two or more of the trench portions; and a second lower end region which is arranged at the first depth position and is arranged at a position not overlapping with the first lower end region, in which the second lower end region includes at least one of a region of a first conductivity type or a region of a second conductivity type which has a lower doping concentration than the first lower end region.

公开(公告)号：US20180269314A1

公开(公告)日：2018-09-20

申请号：US15983040

申请日：2018-05-17

申请人： FUJI ELECTRIC CO., LTD.

发明人： Toru MURAMATSU ,  Hong-fei LU ,  Haruo NAKAZAWA

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7395 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/417 ,  H01L29/66333

摘要： A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.

公开(公告)号：US20170054008A1

公开(公告)日：2017-02-23

申请号：US15232825

申请日：2016-08-10

申请人： FUJI ELECTRIC CO., LTD.

发明人： Toru MURAMATSU ,  Hong-fei LU ,  Haruo NAKAZAWA

IPC分类号： H01L29/739 ,  H01L21/265 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7395 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/417 ,  H01L29/66333

摘要： A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.

摘要翻译： 提供一种半导体器件，所述半导体器件包括形成在其表面侧上的具有MOS栅极结构的第一导电类型的基极层，形成在所述基极层的背面侧上的第二导电类型的集电极层， 并且注入与第一掺杂剂不同的第一掺杂剂和第二掺杂剂，以及形成在集电体层的背面侧的集电极，其中第二掺杂剂的杂质浓度峰位于 集电极层的后表面比第一掺杂剂的杂质浓度峰值以及第二掺杂剂的杂质浓度峰值的大小大于第一掺杂剂的杂质浓度峰值的1/100。

公开(公告)号：US20140111270A1

公开(公告)日：2014-04-24

申请号：US13863374

申请日：2013-04-15

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hong-fei LU

IPC分类号： H01L29/739 ,  H03K17/66 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/32 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66333 ,  H01L29/66348 ,  H02M7/487 ,  H03K17/567 ,  H03K17/66

摘要： An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an n− drift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the n− drift region and a p collector region, and extends between the n− drift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.

摘要翻译： A-NPC电路被配置为使得两个连接的IGBT的中间电位被包括两个RB-IGBT的双向开关钳位。 在RB-IGBT的反向恢复期间，对IGBT的导通di / dt进行控制。 构成双向开关的每个RB-IGBT中的n漂移区域的载流子寿命比典型的NPT结构器件中的载流子寿命相对较长。 在n漂移区域和p集电极区域之间的界面中还提供低寿命区域，并且在n漂移区域和p集电极区域之间延伸。 因此，可以提供低损耗半导体器件，半导体器件的制造方法和半导体器件的控制方法，其中反向恢复损耗减小，而反向恢复电流峰值和跳变电压峰值在 反向恢复被抑制。

公开(公告)号：US20210021204A1

公开(公告)日：2021-01-21

申请号：US17064718

申请日：2020-10-07

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hong-fei LU

IPC分类号： H02M7/00 ,  H02M1/32 ,  H02M1/00 ,  H02M7/537

摘要： A power conversion apparatus includes N semiconductor modules respectively including a switch part including first and second semiconductor switches coupled in series, and an output terminal coupled to a node that connects the first and second semiconductor switches, where N is an integer greater than or equal to 3, wherein the N semiconductor modules are arranged so that the output terminals thereof are adjacent to each other. The power conversion apparatus further includes an output bar to couple the output terminals of the N semiconductor modules so that a parasitic inductance of a current path coupling the output terminals of first and second semiconductor modules among the N semiconductor modules, and a parasitic inductance of a current path coupling the output terminals of the first and third semiconductor modules among the N semiconductor modules, are approximately balanced.

公开(公告)号：US20150014742A1

公开(公告)日：2015-01-15

申请号：US14505659

申请日：2014-10-03

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hong-fei LU

IPC分类号： H01L29/739 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7393 ,  H01L21/225 ,  H01L21/2255 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7397

摘要： Depth of a termination p base region provided in a termination portion of an active region close to an edge termination structure portion is more than depth of a p-type base region provided inside the termination p base region. An n-type high-concentration region is provided from one main surface of the semiconductor substrate in the entire surface layer of one surface of a semiconductor substrate within a depth of 20 μm or less below the bottom of the termination p base region. Ratio of the impurity concentration n1 of the n-type high-concentration region (1c) to the impurity concentration n2 of an n− drift region satisfies 1.0

摘要翻译： 设置在靠近边缘终端结构部分的有源区域的终端部分中的端子p基极区域的深度大于设置在端子p基极区域内的p型基极区域的深度。 在半导体衬底的一个表面的整个表面层的一个主表面上，在端子p基底区域的底部之下的20μm以下的深度内设置n型高浓度区域。 n型高浓度区域（1c）的杂质浓度n1与n漂移区域的杂质浓度n2的比率满足1.0

公开(公告)号：US20140246721A1

公开(公告)日：2014-09-04

申请号：US14274170

申请日：2014-05-09

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hong-fei LU

IPC分类号： H01L29/78

CPC分类号： H01L29/7818 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

摘要： A semiconductor device including: a first conductivity type n-type drift layer; a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer; a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer; and a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer. Thus, it is possible to provide a semiconductor device having a stable and high breakdown voltage termination structure in which the length of a termination structure region is small as well as the immunity to the influence of external charge is high.

摘要翻译： 一种半导体器件，包括：第一导电型n型漂移层; 第二导电型VLD区，形成在设置在n型漂移层的一个主表面上并且浓度高于n型漂移层的端接结构区域的芯片内周侧上; 第二导电类型的第一夹层，形成在VLD区的芯片外周侧，以便与VLD区分离，并且其浓度高于n型漂移层; 以及第一导电型沟道阻挡层，其形成在所述第一夹层的芯片外周侧，以与所述第一夹层分离并且其浓度高于所述n型漂移层。 因此，可以提供一种具有稳定和高耐压端接结构的半导体器件，其中端接结构区域的长度小，并且对外部电荷的影响的抗扰度高。