公开(公告)号：US08309416B2

公开(公告)日：2012-11-13

申请号：US12649684

申请日：2009-12-30

申请人： Eun-Shil Park ,  Yong-Seok Eun ,  Kee-Jeung Lee ,  Min-Soo Kim

发明人： Eun-Shil Park ,  Yong-Seok Eun ,  Kee-Jeung Lee ,  Min-Soo Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10885 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.

摘要翻译： 具有降低的掩埋位线电阻的半导体器件及其制造方法。 半导体器件的制造方法包括蚀刻半导体衬底以形成多个有源区，它们之间形成沟槽，在每个有源区的侧壁上形成侧接触，并形成金属位线 填充相应沟槽的一部分并连接到侧触点。

公开(公告)号：US20120217619A1

公开(公告)日：2012-08-30

申请号：US13338365

申请日：2011-12-28

申请人： Min-Soo Kim ,  Yong-Seok Eun ,  Kee-Jeung Lee ,  Eun-Shil Park ,  Tae-Yoon Kim

发明人： Min-Soo Kim ,  Yong-Seok Eun ,  Kee-Jeung Lee ,  Eun-Shil Park ,  Tae-Yoon Kim

IPC分类号： H01L29/02 ,  H01L21/28

CPC分类号： H01L27/10823 ,  H01L27/10876

摘要： A semiconductor device includes a triangle prism pillar having a first, a second, and a third sidewall surface, a bit line contacted with the first sidewall surface of the pillar, and a word line adjacent to the second sidewall surface of the pillar over the bit line.

摘要翻译： 一种半导体器件包括具有第一，第二和第三侧壁表面的三角形棱柱柱，与柱的第一侧壁表面接触的位线，以及与位于柱上的柱的第二侧壁表面相邻的字线 线。

公开(公告)号：US20110129974A1

公开(公告)日：2011-06-02

申请号：US12830066

申请日：2010-07-02

申请人： Yong-Seok Eun ,  Eun-Shil Park ,  Tae-Yoon Kim ,  Min-Soo Kim

发明人： Yong-Seok Eun ,  Eun-Shil Park ,  Tae-Yoon Kim ,  Min-Soo Kim

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L27/10885 ,  H01L21/743 ,  H01L27/10888

摘要： A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming a plurality of buried bit lines in the first trenches, forming a plurality of second trenches to expose at least one sidewall of the buried bit lines by etching the substrate, and forming a plurality of one-sidewall contact plugs which fill the second trenches.

摘要翻译： 一种制造半导体器件的方法包括：通过蚀刻衬底形成多个第一沟槽，在第一沟槽中形成多个掩埋位线，形成多个第二沟槽，以通过蚀刻暴露掩埋位线的至少一个侧壁 并且形成填充第二沟槽的多个单侧壁接触塞。

公开(公告)号：US08129244B2

公开(公告)日：2012-03-06

申请号：US12830066

申请日：2010-07-02

申请人： Yong-Seok Eun ,  Eun-Shil Park ,  Tae-Yoon Kim ,  Min-Soo Kim

发明人： Yong-Seok Eun ,  Eun-Shil Park ,  Tae-Yoon Kim ,  Min-Soo Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/10885 ,  H01L21/743 ,  H01L27/10888

摘要： A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming a plurality of buried bit lines in the first trenches, forming a plurality of second trenches to expose at least one sidewall of the buried bit lines by etching the substrate, and forming a plurality of one-sidewall contact plugs which fill the second trenches.

摘要翻译： 一种制造半导体器件的方法包括：通过蚀刻衬底形成多个第一沟槽，在第一沟槽中形成多个掩埋位线，形成多个第二沟槽，以通过蚀刻暴露掩埋位线的至少一个侧壁 并且形成填充第二沟槽的多个单侧壁接触塞。

公开(公告)号：US20060240678A1

公开(公告)日：2006-10-26

申请号：US11155261

申请日：2005-06-17

申请人： Min Jang ,  Dong Lee ,  Eun-Shil Park ,  Kwang Jeon ,  Seung Shin ,  Choon Ryu

发明人： Min Jang ,  Dong Lee ,  Eun-Shil Park ,  Kwang Jeon ,  Seung Shin ,  Choon Ryu

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247

摘要： A method of manufacturing a semiconductor device includes forming a LP-CVD oxide film on sides of a gate including a metal film by means of a LP-CVD method that does not cause oxidization of the metal film. Oxidization of a metal film can be prevented physically, and degradation of the electrical device characteristics can be prevented.

摘要翻译： 一种制造半导体器件的方法包括：通过不引起金属膜氧化的LP-CVD法，在包括金属膜的栅极的侧面上形成LP-CVD氧化物膜。 可以物理地防止金属膜的氧化，并且可以防止电气装置特性的劣化。

公开(公告)号：US20130240965A1

公开(公告)日：2013-09-19

申请号：US13494333

申请日：2012-06-12

申请人： Eun-Shil Park ,  Ju-Hyun Myung

发明人： Eun-Shil Park ,  Ju-Hyun Myung

IPC分类号： H01L27/088 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/10885

摘要： A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer.

摘要翻译： 一种制造半导体器件的方法包括：通过垂直蚀刻半导体衬底形成具有两个侧壁的至少一个主体，形成具有露出部分的保护层，该部分露出主体两侧壁的部分，形成填充开口部分的缓冲层 并且通过在缓冲层之间硅化缓冲层和身体的一部分而在体内形成掩埋位线。

公开(公告)号：US07648923B2

公开(公告)日：2010-01-19

申请号：US11963907

申请日：2007-12-24

申请人： Eun-Shil Park ,  Kwon Hong ,  Jae Hong Kim ,  Jae Hyoung Koo

发明人： Eun-Shil Park ,  Kwon Hong ,  Jae Hong Kim ,  Jae Hyoung Koo

IPC分类号： H01L21/31

CPC分类号： H01L21/3144 ,  H01L21/022 ,  H01L21/02326 ,  H01L21/02337 ,  H01L27/11517

摘要： A method of fabricating a flash memory device is disclosed. The method comprises forming a first insulating layer on a semiconductor substrate; accumulating nitrogen at an interface between the semiconductor substrate and the first insulating layer to form a second insulating layer at the interface; and implanting oxygen into the second insulating layer to convert the second insulating layer to a third insulating layer.

摘要翻译： 公开了一种制造闪速存储器件的方法。 该方法包括在半导体衬底上形成第一绝缘层; 在所述半导体衬底和所述第一绝缘层之间的界面处积累氮以在所述界面处形成第二绝缘层; 以及将氧注入到所述第二绝缘层中，以将所述第二绝缘层转换成第三绝缘层。

公开(公告)号：US08860127B2

公开(公告)日：2014-10-14

申请号：US13605550

申请日：2012-09-06

申请人： Heung-Jae Cho ,  Eui-Seong Hwang ,  Eun-Shil Park

发明人： Heung-Jae Cho ,  Eui-Seong Hwang ,  Eun-Shil Park

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/28026 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/7827

摘要： A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.

摘要翻译： 一种用于制造垂直沟道晶体管的方法，包括在衬底上形成横向相对的两个侧壁的多个柱; 在支柱的两个侧壁上形成栅介电层; 形成覆盖所述柱的任何一个侧壁的第一栅电极和覆盖所述柱的其它侧壁并且具有低于所述第一栅电极的高度的屏蔽栅电极; 以及形成与所述第一栅电极的侧壁的上部连接的第二栅电极。

公开(公告)号：US08836001B2

公开(公告)日：2014-09-16

申请号：US13494333

申请日：2012-06-12

申请人： Eun-Shil Park ,  Ju-Hyun Myung

发明人： Eun-Shil Park ,  Ju-Hyun Myung

IPC分类号： H01L27/08 ,  H01L29/94

CPC分类号： H01L27/10885

摘要： A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer.

摘要翻译： 一种制造半导体器件的方法包括：通过垂直蚀刻半导体衬底形成具有两个侧壁的至少一个主体，形成具有露出部分的保护层，该部分露出本体的两个侧壁的部分，形成填充开口部分的缓冲层 并且通过在缓冲层之间硅化缓冲层和身体的一部分而在体内形成掩埋位线。

公开(公告)号：US20130320433A1

公开(公告)日：2013-12-05

申请号：US13605550

申请日：2012-09-06

申请人： Heung-Jae CHO ,  Eui-Seong Hwang ,  Eun-Shil Park

发明人： Heung-Jae CHO ,  Eui-Seong Hwang ,  Eun-Shil Park

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/28026 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/7827

摘要： A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.