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    SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR
    1.
    发明申请
    SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR 有权

    公开(公告)号：US20230102625A1

    公开(公告)日：2023-03-30

    申请号：US17529817

    申请日：2021-11-18

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Byung-Do YANG ,  Sooji NAM ,  Jaehyun MOON ,  Jae-Eun PI ,  Jae-Min KIM

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/417

    Abstract: Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.

    CMOS LOGIC ELEMENT INCLUDING OXIDE SEMICONDUCTOR
    2.
    发明申请
    CMOS LOGIC ELEMENT INCLUDING OXIDE SEMICONDUCTOR 有权

    公开(公告)号：US20230097393A1

    公开(公告)日：2023-03-30

    申请号：US17520853

    申请日：2021-11-08

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Byung-Do YANG ,  Sooji NAM ,  Jaehyun MOON ,  Jae-Eun PI ,  Jae-Min KIM

    IPC: H01L27/092 ,  H01L29/24 ,  H03K19/0185 ,  H03K19/0948 ,  H01L27/02

    Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

    SPIKE NEURAL NETWORK CIRCUIT
    3.
    发明公开
    SPIKE NEURAL NETWORK CIRCUIT 审中-公开

    公开(公告)号：US20230385620A1

    公开(公告)日：2023-11-30

    申请号：US18125553

    申请日：2023-03-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Byung-Do YANG ,  Dongwon LEE ,  Jae-Jin LEE

    IPC: G06N3/063 ,  G06N3/049

    CPC classification number: G06N3/063 ,  G06N3/049

    Abstract: Disclosed is a spike neural network circuit which includes a pulse generator that receives an input spike signal and generates a first modulation pulse and a second modulation pulse based on the input spike signal, first and second current source arrays controlled based on a weight memory, a membrane capacitor, a first switch that delivers a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse, and a second switch that delivers a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.

    SPIKE NEURAL NETWORK CIRCUIT INCLUDING INPUT SPIKE DETECTING CIRCUIT AND OPERATING METHOD THEREOF
    5.
    发明公开
    SPIKE NEURAL NETWORK CIRCUIT INCLUDING INPUT SPIKE DETECTING CIRCUIT AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20230385618A1

    公开(公告)日：2023-11-30

    申请号：US18307196

    申请日：2023-04-26

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Byung-Do YANG ,  Dongwon LEE ,  Jae-Jin LEE

    IPC: G06N3/049 ,  G06N3/063

    CPC classification number: G06N3/049 ,  G06N3/063

    Abstract: Disclosed is a spike neural network circuit including a synaptic circuit including synapses arranged in rows and columns, an axon circuit that generates a first input spike signal to be provided to a first row among the rows, and a second input spike signal to be provided to a second row among the rows, an input spike detecting circuit that generates an enable signal when detecting a pulse from at least one of the first input spike signal and the second input spike signal, and a first neuron circuit that compares a voltage level of a first accumulated signal, which is output from a first column among the columns, with a threshold voltage level in response to the enable signal, and outputs a first output spike signal when the voltage level of the first accumulated signal exceeds the threshold voltage level.

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