公开(公告)号：US20220321127A1

公开(公告)日：2022-10-06

申请号：US17468853

申请日：2021-09-08

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Mun OH ,  Byung-Do YANG ,  Jung-Ho KIM

IPC: H03K19/1776 ,  H03K19/17784

Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.