公开(公告)号：US20230016751A1

公开(公告)日：2023-01-19

申请号：US17501910

申请日：2021-10-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Mun OH

IPC: G11C7/24

Abstract: Disclosed herein is an apparatus for hardware metering using a memory-type camouflaged cell. The apparatus includes memory including at least one camouflaged memory cell in which a key is hidden by a designer in advance and a controller for controlling whether to block the supply of power to the memory. The controller may perform reading a key from a corresponding key location in the multiple memory cells of the memory based on key location information stored in the controller when a key is input from the outside, determining whether the key input from the outside is the same as the key read from the memory, setting an authentic flag based on the determination result, and performing control based on the set authentic flag such that the memory operates normally or the supply of power is blocked.

公开(公告)号：US20240177753A1

公开(公告)日：2024-05-30

申请号：US18432390

申请日：2024-02-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Mun OH

IPC: G11C7/24

CPC classification number: G11C7/24

Abstract: Disclosed herein is an apparatus for hardware metering using a memory-type camouflaged cell. The apparatus includes memory including at least one camouflaged memory cell in which a key is hidden by a designer in advance and a controller for controlling whether to block the supply of power to the memory. The controller may perform reading a key from a corresponding key location in the multiple memory cells of the memory based on key location information stored in the controller when a key is input from the outside, determining whether the key input from the outside is the same as the key read from the memory, setting an authentic flag based on the determination result, and performing control based on the set authentic flag such that the memory operates normally or the supply of power is blocked.

公开(公告)号：US20220321127A1

公开(公告)日：2022-10-06

申请号：US17468853

申请日：2021-09-08

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Mun OH ,  Byung-Do YANG ,  Jung-Ho KIM

IPC: H03K19/1776 ,  H03K19/17784

Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.