公开(公告)号：US4849662A

公开(公告)日：1989-07-18

申请号：US851805

申请日：1986-04-14

Applicant: Douglas R. Holberg ,  Eric J. Swanson

Inventor： Douglas R. Holberg ,  Eric J. Swanson

IPC: H03H19/00 ,  H03H15/02 ,  H03H9/64

CPC classification number: H03H19/00

Abstract: A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.

公开(公告)号：US07256611B2

公开(公告)日：2007-08-14

申请号：US11005700

申请日：2004-12-07

Applicant: Douglas R. Holberg ,  Kenneth W. Fernald

Inventor： Douglas R. Holberg ,  Kenneth W. Fernald

IPC: H03K19/177

CPC classification number: H03K19/1731

Abstract: A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.

Abstract translation: 交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。 使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个 单元由控制输入。

公开(公告)号：US06879004B2

公开(公告)日：2005-04-12

申请号：US10288188

申请日：2002-11-05

Applicant: Ka Y. Leung ,  Douglas R. Holberg

Inventor： Ka Y. Leung ,  Douglas R. Holberg

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A spark gap device for protecting an integrated circuit. The spark gap device includes a first node for receiving an input signal and a second node to be protected. A first conductive layer is conductively interfaced to the first node and the second node and disposed therebetween. A second conductive layer is connected to a sink voltage and separated from the first conductive layer by an insulating layer of a predetermined thickness. A portion of the first conductive layer is disposed proximate to the second conductive layer and not overlying the second conductive layer, such that a gap is formed therebetween and the gap having a dimension that is greater than the thickness of the insulating layer.

Abstract translation: 一种用于保护集成电路的火花隙装置。 火花隙装置包括用于接收输入信号的第一节点和待保护的第二节点。 第一导电层导电地接合到第一节点和第二节点并且设置在它们之间。 第二导电层连接到宿电压，并通过预定厚度的绝缘层与第一导电层分离。 第一导电层的一部分设置成靠近第二导电层并且不覆盖第二导电层，使得在其间形成间隙，并且间隙的尺寸大于绝缘层的厚度。

公开(公告)号：US06724336B2

公开(公告)日：2004-04-20

申请号：US10141462

申请日：2002-05-07

Applicant: Ka Y. Leung ,  Douglas R. Holberg

Inventor： Ka Y. Leung ,  Douglas R. Holberg

IPC: H03M166

CPC classification number: H03M1/0602 ,  H03M1/682 ,  H03M1/765

Abstract: A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.

Abstract translation: 具有串联连接的晶体管的数模转换器形成用于各个分段电阻串的高阻抗电流源。 形成用于一个电阻器串的电流吸收器的串联晶体管通过利用负反馈放大器呈现高输出阻抗。 通过使用适当的增益电阻配置输出放大器，可以消除一个电阻串中的裕量电阻和偏移电阻的影响。 通过使用相同值的主电阻和子电阻串的所有电阻，可以实现高精度的D / A转换。

公开(公告)号：US06288661B1

公开(公告)日：2001-09-11

申请号：US09419148

申请日：1999-10-15

Applicant: Douglas R. Holberg

Inventor： Douglas R. Holberg

IPC: H03M166

CPC classification number: H03M1/682 ,  H03M1/46 ,  H03M1/765

Abstract: An analog-to-digital converter having a digital-to-analog converter section for converting a Z-bit digital word. The digital-to-analog converter section includes an MSB portion for receiving a predetermined portion of the upper most significant bits, M bits, of the digital word and providing a monotonic division, VINC, of a reference voltage to provide a first analog voltage. A SubDAC portion is provided for receiving the remaining portion of the digital word, N bits, and providing a monotonic division of the voltage VINC to provide a second analog voltage. A summing device sums the first analog voltage with the second analog voltage to provide an analog output voltage with an M+N bit resolution, Z=M+N.

Abstract translation: 一种具有用于转换Z位数字字的数模转换器部分的模数转换器。 数模转换器部分包括MSB部分，用于接收数字字的最高有效位M位的预定部分，并提供参考电压的单调除法VINC以提供第一模拟电压。 提供SubDAC部分用于接收数字字的剩余部分N位，并且提供电压VINC的单调除法以提供第二模拟电压。 求和装置将第一模拟电压与第二模拟电压相加，以提供具有M + N位分辨率的模拟输出电压，Z = M + N。

公开(公告)号：US07504900B2

公开(公告)日：2009-03-17

申请号：US11694624

申请日：2007-03-30

Applicant: Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

Inventor： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC: G06F1/04 ,  H03B5/00 ,  H03B5/12 ,  H03B5/24 ,  H03B5/36

CPC classification number: G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract translation: 集成电路封装包括处理核心和内部振荡器。 处理核心通过一组指令来执行预定义的过程。 内部振荡器为集成电路封装提供系统时钟。 内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

公开(公告)号：US07382181B2

公开(公告)日：2008-06-03

申请号：US11623686

申请日：2007-01-16

Applicant: Golam R. Chowdhury ,  Douglas R. Holberg

Inventor： Golam R. Chowdhury ,  Douglas R. Holberg

IPC: H03K5/00

CPC classification number: H03H11/04 ,  H03B5/14 ,  H03F1/342 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45366 ,  H03L7/0995

Abstract: A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.

Abstract translation: 公开了一种用于提供可调GMC滤波器的系统和方法，其中具有与其反馈回路中的衰减器的跨导元件被允许以第一振荡频率振荡。 滤波器的输入使振荡频率调谐到预定频率。

公开(公告)号：US07323855B2

公开(公告)日：2008-01-29

申请号：US11095844

申请日：2005-03-31

Applicant: Jinwen Xiao ,  Ka Y. Leung ,  Douglas R. Holberg

Inventor： Jinwen Xiao ,  Ka Y. Leung ,  Douglas R. Holberg

IPC: G05F1/46 ,  G05F1/62

CPC classification number: H02M3/33515 ,  H02M3/33576 ,  H02M2001/0012

Abstract: A DC-DC digital pulse width modulated power supply is disclosed for generating a DC regulated output voltage. A digital control node has a digital control voltage disposed thereon for controlling the operation of the supply, wherein the digital control voltage has a substantially zero voltage when the output voltage of the supply is at a desired regulation, the digital control voltage having a resolution defined by a least significant bit (LSB). An input node receives a DC analog reference voltage defining the output voltage of the supply. A difference device determines the difference between the analog reference voltage and the output voltage to generate said digital control voltage. An LSB variation device varies the size of the LSB without varying the value of the digital control voltage for a substantially zero difference between the analog reference voltage and the output voltage.

Abstract translation: 公开了用于产生直流调节输出电压的DC-DC数字脉宽调制电源。 数字控制节点具有设置在其上用于控制电源的操作的数字控制电压，其中当电源的输出电压处于期望的调节时，数字控制电压具有基本为零的电压，数字控制电压具有定义的分辨率 通过最低有效位（LSB）。 输入节点接收限定电源的输出电压的DC模拟参考电压。 差分装置确定模拟参考电压和输出电压之间的差异，以产生所述数字控制电压。 LSB变化装置改变LSB的大小，而不改变模拟参考电压和输出电压之间的基本上零差的数字控制电压的值。

公开(公告)号：US07304679B1

公开(公告)日：2007-12-04

申请号：US10742170

申请日：2003-12-19

Applicant: Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

Inventor： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

IPC: H04N5/222 ,  H04N5/235 ,  H04N5/20 ,  H03M1/12

CPC classification number: H03M1/002 ,  H03M1/007 ,  H03M1/12 ,  H04N5/232 ,  H04N5/23245

Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.

Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

公开(公告)号：US06891487B2

公开(公告)日：2005-05-10

申请号：US10752913

申请日：2004-01-07

Applicant: Ka Y. Leung ,  Douglas R. Holberg ,  Kafai Leung

Inventor： Ka Y. Leung ,  Douglas R. Holberg ,  Kafai Leung

IPC: G06F13/28 ,  H01C10/16 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/38 ,  H03M1/46 ,  H03M1/66 ,  H03M1/78

CPC classification number: H03M1/1057 ,  H03M1/468

Abstract: Capacitor calibration in SAR converter. A method for calibrating a switched capacitor array in a SAR data converter is disclosed, which array includes a plurality of primary capacitors having a common node plate interfaced to a common node and a switched plate interfaced to a switch that is operable to be switched between first and second reference voltages. A comparator having an input connected to the common node and a reference input connected to a comparator reference node receives a comparator reference voltage. In a first calibration step for calibrating one of the primary capacitors, a reference capacitor is provided and then, the switched plate of the select primary capacitor is connected to the first reference voltage, the switched plate of the other capacitors and the reference capacitor are connected to the second reference voltage, and the common node and the comparator reference node are driven with a driver to dispose a first voltage thereon. In a second calibration step, the common node is allowed to float, the switched plate of the select primary capacitor is connected to the second reference voltage, the switched plate of the reference capacitor is connected to the first reference voltage, and the voltage on the common node is compared to the first voltage on the comparator reference node. A determination is then made as to whether the voltage on the common node is greater than the first voltage. A plurality of trim capacitors are provided and, if in the second calibration step, the voltage on the common node was determined to be greater than the first voltage, then one of the trim capacitors is disposed in parallel with the select one of the primary capacitors and then the first and second calibrating steps are repeated.

Abstract translation: SAR转换器中的电容校准。 公开了一种用于校准SAR数据转换器中的开关电容器阵列的方法，该阵列包括具有与公共节点接口的公共节点板的多个初级电容器和与开关接口的开关板，该开关板可操作以在第一 和第二参考电压。 具有连接到公共节点的输入和连接到比较器参考节点的参考输入的比较器接收比较器参考电压。 在用于校准主电容器之一的第一校准步骤中，提供参考电容器，然后，选择一次电容器的开关板连接到第一参考电压，另一电容器的开关板和参考电容器连接 到第二参考电压，并且公共节点和比较器参考节点由驱动器驱动以在其上设置第一电压。 在第二校准步骤中，允许公共节点浮动，选择主电容器的开关板连接到第二参考电压，参考电容器的开关板连接到第一参考电压，并且在 公共节点与比较器参考节点上的第一个电压进行比较。 然后确定公共节点上的电压是否大于第一电压。 提供多个修整电容器，如果在第二校准步骤中，将公共节点上的电压确定为大于第一电压，则将一个修整电容器与主电容器中的选择一个平行设置 然后重复第一和第二校准步骤。