公开(公告)号：US20240290616A1

公开(公告)日：2024-08-29

申请号：US18435035

申请日：2024-02-07

Applicant: DENSO CORPORATION ,  FUJI ELECTRIC CO., LTD.

Inventor： Tomohiro MIMURA ,  Kensuke HATA ,  Masanobu IWAYA

IPC: H01L21/04 ,  H01L23/34 ,  H01L29/06 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/045 ,  H01L21/046 ,  H01L23/34 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813

Abstract: A silicon carbide semiconductor device has a semiconductor substrate, a trench gate structure disposed in the semiconductor substrate, a first electrode electrically connected to an impurity region and a bae layer of the semiconductor substrate, a second electrode connected to a substrate, and an interlayer insulating film disposed between a gate electrode and the first electrode. The trench gate structure includes a gate insulating film disposed in a trench of the semiconductor substrate and the gate electrode disposed on the gate insulating film. A portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one of nitrogen, hydrogen or phosphorous. The interlayer insulating film has a contact insulating film that is in contact with the gate electrode. The contact insulating film is provided by a deposited film.

公开(公告)号：US20230074595A1

公开(公告)日：2023-03-09

申请号：US17889350

申请日：2022-08-16

Applicant: FUJI ELECTRIC CO., LTD. ,  DENSO Corporation

Inventor： Masayuki MIYAZAKI ,  Taketo TSUJI ,  Makoto TERAKAWA ,  Kensuke HATA ,  Tomohiro MIMURA

IPC: G01N21/95 ,  H01L21/66

Abstract: Provided is a manufacturing method of a semiconductor device having a semiconductor substrate. The manufacturing method includes forming an interlayer insulating film above the semiconductor substrate; forming a metal electrode above the interlayer insulating film; acquiring an image of the metal electrode and detecting defect candidates on a surface of the metal electrode based on the image; and performing inspection by determining a quality of the semiconductor device, based on height information of each of the detected defect candidates in a direction perpendicular to the surface of the metal electrode.

公开(公告)号：US20210151385A1

公开(公告)日：2021-05-20

申请号：US17159610

申请日：2021-01-27

Applicant: DENSO CORPORATION

Inventor： Aiko KAJI ,  Haruhito ICHIKAWA ,  Shuhei MITANI ,  Tomohiro MIMURA ,  Yukihiro WAKASUGI ,  Narumasa SOEJIMA

IPC: H01L23/544 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes: forming an insulating film on a surface of a semiconductor layer of a semiconductor substrate; forming a contact hole in the insulating film; forming a conductor material on the insulating film to be in contact with the semiconductor layer through the contact hole; and patterning the conductor material using an alignment key included in the conductor material.

公开(公告)号：US20140353683A1

公开(公告)日：2014-12-04

申请号：US14287585

申请日：2014-05-27

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hisashi ISHIMABUSHI ,  Tomohiro MIMURA ,  Narumasa SOEJIMA

IPC: H01L21/265 ,  H01L29/16

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/6606 ,  H01L29/7802 ,  H01L29/78642 ,  H01L29/861 ,  H01L29/872

Abstract: In a semiconductor substrate preparation step, a semiconductor substrate which is made of SiC and in which a first semiconductor region of a first conductivity type is formed is prepared. In a second semiconductor region forming step, a second semiconductor region is formed by implanting an impurity of a second conductivity type into a first semiconductor region through multiple ion implantation steps while varying implantation depths of the respective multiple ion implantation steps. In the second semiconductor region forming step, a dose amount of the impurity when an implantation energy of multiple ion implantation steps is the largest is smaller than a dose amount of impurity when the implantation energy is not the largest.

Abstract translation: 在半导体衬底制备步骤中，制备由SiC制成并且其中形成第一导电类型的第一半导体区域的半导体衬底。 在第二半导体区域形成步骤中，通过在改变多个离子注入步骤的注入深度的同时通过多个离子注入步骤将第二导电类型的杂质注入到第一半导体区域中形成第二半导体区域。 在第二半导体区域形成步骤中，当多个离子注入步骤的注入能量最大时，杂质的剂量量小于当注入能量不是最大时的杂质的剂量。