公开(公告)号：US20080224752A1

公开(公告)日：2008-09-18

申请号：US12045125

申请日：2008-03-10

Applicant: Chul-Ho LEE ,  Jin-Yub LEE

Inventor： Chul-Ho LEE ,  Jin-Yub LEE

IPC: G06F1/04

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/14

Abstract: An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

Abstract translation: 公开了一种产生内部时钟的内部时钟发生器，系统和方法。 该方法包括检测系统内的工作电压的电平，将工作电压的电平与目标电压电平进行比较，并产生相应的检测信号，以及选择正常时钟和具有比周期长的周期的备用时钟 的相对于检测信号的正常时钟，并且基于该选择产生内部时钟。

公开(公告)号：US20080163030A1

公开(公告)日：2008-07-03

申请号：US11874821

申请日：2007-10-18

Applicant: Jin-Yub LEE

Inventor： Jin-Yub LEE

IPC: G06F11/14 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G11C16/10 ,  G11C16/26

Abstract: The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

Abstract translation: 本公开是在页面复制操作期间具有错误检查和校正功能的NAND闪存。 NAND闪存能够禁止从源页面将错误位转录到重复页面。 本发明的闪速存储器的实施例包括用于校正存储在页缓冲器中的源数据的位错误的校正电路，配置成将源数据提供给校正电路并向校页电路提供校正数据的电路，以及配置 将源数据复制到页面缓冲器，并将校正数据存储在页面缓冲器的另一页中。

公开(公告)号：US20080266983A1

公开(公告)日：2008-10-30

申请号：US12025117

申请日：2008-02-04

Applicant: Jin-Kook KIM ,  Jin-Yub LEE

Inventor： Jin-Kook KIM ,  Jin-Yub LEE

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory device includes a memory cell array, a bulk voltage generator and a controller. The memory cell array is formed in a bulk area and including memory cells arranged in rows and columns. The bulk voltage generator is configured to supply a bulk voltage to the bulk area. The controller is configured to control the bulk voltage generator to vary an erase time based on a time when the bulk voltage reaches a target voltage.

Abstract translation: 闪存器件包括存储单元阵列，体电压发生器和控制器。 存储单元阵列形成在大块区域中并且包括以行和列排列的存储单元。 体电压发生器被配置为向体积区域提供体电压。 控制器被配置为基于体电压达到目标电压的时间来控制体电压发生器来改变擦除时间。

公开(公告)号：US20080084749A1

公开(公告)日：2008-04-10

申请号：US11844514

申请日：2007-08-24

Applicant: Jin-wook LEE ,  Jin-Yub LEE

Inventor： Jin-wook LEE ,  Jin-Yub LEE

IPC: G11C16/00

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller generates a program voltage control signal according to program/erase operations information. The voltage controller generates a program voltage in response to the program voltage control signal.

Abstract translation: 提供了用于产生编程电压的电路和方法，以及使用其的非易失性存储器件。 产生用于对半导体存储器件的存储单元进行编程的编程电压的电路包括编程电压控制器和电压产生单元。 程序电压控制器根据编程/擦除操作信息产生编程电压控制信号。 电压控制器响应于编程电压控制信号产生编程电压。

公开(公告)号：US20090175087A1

公开(公告)日：2009-07-09

申请号：US12247288

申请日：2008-10-08

Applicant: Min-Gun PARK ,  Jin-Yub LEE

Inventor： Min-Gun PARK ,  Jin-Yub LEE

IPC: G11C16/06

CPC classification number: G11C16/3454 ,  G11C16/0483

Abstract: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Abstract translation: 提供了一种用于验证闪存设备的编程操作的方法。 闪速存储器件包括串联选择晶体管，多个存储单元和地选择晶体管串联连接的至少一个存储器串，并且相对于存储器串中的所选存储单元执行编程操作。 该方法包括将串联选择晶体管的阈值电压加到电源电压而获得的电压施加到连接到串选择晶体管的串选择线; 对连接到每个存储单元的字线和连接到地选择晶体管的接地选择线施加接地电压; 将连接到存储器串的位线预充电到电源电压; 以及确定所选存储单元的编程操作是否完成。

公开(公告)号：US20100001710A1

公开(公告)日：2010-01-07

申请号：US12476565

申请日：2009-06-02

Applicant: Joon Young KWAK ,  Yoon-Hee CHOI ,  Jin-Yub LEE ,  You-Sang LEE ,  Bo-Geun KIM

Inventor： Joon Young KWAK ,  Yoon-Hee CHOI ,  Jin-Yub LEE ,  You-Sang LEE ,  Bo-Geun KIM

IPC: G05F3/16

CPC classification number: G05F3/08

Abstract: A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

Abstract translation: 参考电压产生电路提供稳定的参考电压并且包括： 提供时钟信号的时钟发生器，响应于时钟信号提供泵浦电压的高电压发生器，通过从所述泵浦电压去除电压纹波提供静态电压的纹波消除器以及提供参考电压的参考电压发生器。

公开(公告)号：US20080055996A1

公开(公告)日：2008-03-06

申请号：US11782746

申请日：2007-07-25

Applicant: Jin-Kook KIM ,  Jin-Yub LEE

Inventor： Jin-Kook KIM ,  Jin-Yub LEE

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/32

Abstract: Embodiments of the present invention provide a flash memory device with a unified oscillation circuit, and a method of operating the device. The unified oscillation circuit produces alternative internal clock signals for corresponding alternative operating modes of the flash memory device. At least a portion of the unified oscillation circuit is used to generate all of the alternative internal clock signals. Compared to conventional memory devices and methods that use multiple oscillators, embodiments of the invention improve circuit density and reduce the incidence of timing glitches caused by switching between multiple oscillators.

Abstract translation: 本发明的实施例提供一种具有统一振荡电路的闪速存储器件，以及操作该器件的方法。 统一的振荡电路产生替代的内部时钟信号，用于闪速存储器件的相应的备选操作模式。 统一振荡电路的至少一部分被用于产生所有备选的内部时钟信号。 与使用多个振荡器的常规存储器件和方法相比，本发明的实施例提高了电路密度并减少了由多个振荡器之间的切换引起的定时毛刺的发生。

公开(公告)号：US20110299332A1

公开(公告)日：2011-12-08

申请号：US13209500

申请日：2011-08-15

Applicant: Pyung-Moon ZHANG ,  Jin-Yub LEE

Inventor： Pyung-Moon ZHANG ,  Jin-Yub LEE

IPC: G11C16/10

CPC classification number: G01R31/3004 ,  G11C29/02 ,  G11C29/021 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56

Abstract: Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.

Abstract translation: 提供了一种测试系统和相关的高电压测量方法。 该方法包括：经由共享信道将外部电压信号施加到多个DUT中的一个或多个，将外部电压信号与由一个或多个DUT内部产生的高电压信号进行比较并产生相应的比较结果， 根据比较结果对各高压信号进行电压电平。

公开(公告)号：US20080316819A1

公开(公告)日：2008-12-25

申请号：US12199834

申请日：2008-08-28

Applicant: Jin-Yub LEE

Inventor： Jin-Yub LEE

IPC: G11C16/04 ,  G11C8/00

CPC classification number: G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641

Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included.

Abstract translation: 提供了能够操纵多位和单位数据的闪速存储器件。 闪存器件可以包括具有多个存储器块的存储单元阵列。 闪存装置还可以包括用于存储指示每个存储块是否是多位存储块的多位/单位信息的判断电路，确定输入块地址的存储块是否为 根据所存储的多位/单位信息的多位存储器块，并输出适当的标志信号。 还包括用于选择性地执行与块地址相对应的存储块的多位和单位读/写操作的读/写电路，以及用于控制读/写电路的控制逻辑，使得读/写 电路可以基于标志信号执行多位或单位读/写操作。 还可以包括包括用于检查和校正读/写电路的数据中的错误的多位ECC单元和单位ECC单元的错误检查和校正（ECC）电路。

公开(公告)号：US20070115727A1

公开(公告)日：2007-05-24

申请号：US11465323

申请日：2006-08-17

Applicant: Yong-Taek JEONG ,  Jin-Yub LEE

Inventor： Yong-Taek JEONG ,  Jin-Yub LEE

IPC: G11C11/34

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

Abstract translation: 闪存器件可以包括泵，用于控制泵的调节器，使得泵的输出电压基本上保持在目标电压，以及控制电路以控制调节器，使得泵选择性地产生编程电压或 擦除电压。 在一些实施例中，泵的输出电压可以在编程操作期间响应于程序循环迭代而阶梯式，或者在擦除操作期间被设置为目标电压。