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    POWER LDMOS TRANSISTOR
    1.
    发明申请
    POWER LDMOS TRANSISTOR 有权
    功率LDMOS晶体管

    公开(公告)号：US20070138548A1

    公开(公告)日：2007-06-21

    申请号：US11676613

    申请日：2007-02-20

    申请人： Christopher Kocon ,  Shuming Xu ,  Jacek Korec

    发明人： Christopher Kocon ,  Shuming Xu ,  Jacek Korec

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823

    摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

    摘要翻译： 横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。 在半导体层中形成第一导电类型的源极区域和漏极延伸区域。 在半导体层中形成第二导电类型的体区。 导电栅极形成在沟道区域上形成的栅极电介质层上。 漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。 漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。 源极触点将源极区域电连接到主体区域。

    Lateral power transistor with self-biasing electrodes
    2.
    发明申请
    Lateral power transistor with self-biasing electrodes 有权
    具有自偏置电极的侧向功率晶体管

    公开(公告)号：US20070187781A1

    公开(公告)日：2007-08-16

    申请号：US11404062

    申请日：2006-04-12

    申请人： Christopher Kocon

    发明人： Christopher Kocon

    IPC分类号： H01L29/76

    CPC分类号： H01L29/407 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/7816 ,  H01L29/7824

    摘要： A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

    摘要翻译： 半导体功率晶体管包括漂移区中的第一导电类型的漂移区和第二导电类型的阱区，使得阱区和漂移区在它们之间形成pn结。 第一导电类型的第一高度掺杂的硅区域在阱区中，并且第二高度掺杂的硅区域在漂移区域中。 第二高掺杂硅区域与阱区域横向间隔开，使得在将晶体管置于导通状态时，电流通过漂移区域在第一和第二高掺杂硅区域之间横向流动。 延伸到垂直于电流的漂移区域中的多个沟槽中的每一个包括衬在至少一部分沟槽侧壁和至少一个导电电极的电介质层。

    Method for improved MOS gating to reduce miller capacitance and switching losses
    4.
    发明申请
    Method for improved MOS gating to reduce miller capacitance and switching losses 有权
    改善MOS门控以减少铣床电容和开关损耗的方法

    公开(公告)号：US20050145934A1

    公开(公告)日：2005-07-07

    申请号：US11052258

    申请日：2005-02-07

    申请人： Christopher Kocon ,  Alan Elbanhawy

    发明人： Christopher Kocon ,  Alan Elbanhawy

    IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7813

    摘要： A method for reducing miller capacitance and switching losses in an integrated circuit includes providing a switching gate electrode having respective portions that are coplanar with the source and well regions of the integrated circuit. The switching gate electrode is configured for switching the integrated circuit on and off in response to a relatively small change in applied voltage. A shielding gate electrode is formed with respective portions coplanar with the switching electrode and the well region. The shielding electrode is configured for charging the gate-to-drain overlap region of the integrated circuit.

    摘要翻译： 一种用于降低集成电路中的磨机电容和开关损耗的方法包括提供具有与集成电路的源区和阱区共面的各部分的开关栅电极。 开关栅电极被配置为响应于施加电压的相对较小的变化而导通和关断集成电路。 屏蔽栅极形成有与开关电极和阱区共面的各个部分。 屏蔽电极被配置为对集成电路的栅极 - 漏极重叠区域进行充电。

    MOS-gated transistor with reduced miller capacitance
    5.
    发明申请
    MOS-gated transistor with reduced miller capacitance 有权
    具有降低的铣刀电容的MOS门控晶体管

    公开(公告)号：US20060076617A1

    公开(公告)日：2006-04-13

    申请号：US10962367

    申请日：2004-10-08

    申请人： Praveen Shenoy ,  Christopher Kocon

    发明人： Praveen Shenoy ,  Christopher Kocon

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

    摘要： In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

    摘要翻译： 在本发明的一个实施例中，沟槽MOS门控晶体管包括形成具有第二导电类型的阱区的pn结的第一导电类型的第一区域。 阱区域具有平坦的底部部分和比平坦的底部部分更深的部分。 栅极沟槽延伸到阱区域中。 通道区域沿着栅极沟槽的外侧壁在阱区域中延伸。 栅极沟槽具有终止于第一区域内的第一底部部分和终止于阱区域较深部分内的第二底部部分，使得当晶体管处于导通状态时，阱区域的较深部分防止电流 从而流过位于井区域较深部分正上方的那些通道区域部分。

    STRUCTURE AND METHOD FOR IMPROVING SHIELDED GATE FIELD EFFECT TRANSISTORS
    6.
    发明申请
    STRUCTURE AND METHOD FOR IMPROVING SHIELDED GATE FIELD EFFECT TRANSISTORS 有权
    用于改进屏蔽栅场效应晶体管的结构和方法

    公开(公告)号：US20080017920A1

    公开(公告)日：2008-01-24

    申请号：US11620002

    申请日：2007-01-04

    申请人： Steven Sapp ,  Ashok Challa ,  Christopher Kocon

    发明人： Steven Sapp ,  Ashok Challa ,  Christopher Kocon

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/7803

    摘要： A field effect transistor is disclosed. In one embodiment, the field effect transistor includes a trench extending into a drift region of the field effect transistor. A shield electrode in a lower portion of the trench is insulated from the drift region by a shield dielectric. A gate electrode in the trench over the shield electrode is insulated from the shield electrode by an inter-electrode dielectric. A source region is formed adjacent the trench. A resistive element is coupled to the shield electrode and to a source region in the field effective transistor.

    摘要翻译： 公开了一种场效应晶体管。 在一个实施例中，场效应晶体管包括延伸到场效应晶体管的漂移区的沟槽。 沟槽下部的屏蔽电极通过屏蔽电介质与漂移区绝缘。 屏蔽电极上的沟槽中的栅电极通过电极间绝缘体与屏蔽电极绝缘。 在沟槽附近形成源区。 电阻元件耦合到屏蔽电极和场有效晶体管中的源极区域。

    Method of Making a MOS-Gated Transistor with Reduced Miller Capacitance
    7.
    发明申请
    Method of Making a MOS-Gated Transistor with Reduced Miller Capacitance 失效
    制造具有降低米勒电容的MOS栅极晶体管的方法

    公开(公告)号：US20070264782A1

    公开(公告)日：2007-11-15

    申请号：US11829262

    申请日：2007-07-27

    申请人： Praveen Shenoy ,  Christopher Kocon

    发明人： Praveen Shenoy ,  Christopher Kocon

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

    摘要： A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

    摘要翻译： 沟槽MOS门控晶体管如下形成。 提供第一导电类型的第一区域。 然后在第一区域的上部形成第二导电类型的阱区域。 形成了延伸穿过阱区并终止于第一区域内的沟槽。 沿着沟槽底部的预定部分注入第二导电类型的掺杂剂，以沿沟槽底部形成与阱区连续的区域，使得当晶体管处于导通状态时，阱区的较深部分 防止电流流过位于阱区域较深部分正上方的那些沟道区域部分。

    Periphery design for charge balance power devices
    8.
    发明申请
    Periphery design for charge balance power devices 有权
    电荷平衡功率器件的周边设计

    公开(公告)号：US20070210341A1

    公开(公告)日：2007-09-13

    申请号：US11375683

    申请日：2006-03-13

    申请人： Chanho Park ,  Joseph Yedinak ,  Christopher Kocon ,  Jason Higgs ,  Jaegil Lee

    发明人： Chanho Park ,  Joseph Yedinak ,  Christopher Kocon ,  Jason Higgs ,  Jaegil Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.

    摘要翻译： 电荷平衡半导体功率器件包括有源区，其具有p柱的条带和以交替方式布置的n个柱的条带，沿着有源区的长度延伸的p和n柱的条带。 非活动周边区域包围有源区域，并且包括围绕有源区域的至少一个p环。 最后一根直立在有源区域边缘上的p柱条的一端终止于大致直线，其中p柱的每条剩余的条的一端也结束。 直线垂直于有源区域的长度延伸，n和p柱的条带沿着该区域的长度延伸。

    MOS-gated device having a buried gate and process for forming same
    10.
    发明申请
    MOS-gated device having a buried gate and process for forming same 有权
    具有掩埋栅极的MOS门控器件及其形成工艺

    公开(公告)号：US20050224868A1

    公开(公告)日：2005-10-13

    申请号：US11091733

    申请日：2005-03-28

    申请人： Christopher Kocon ,  Jun Zeng

    发明人： Christopher Kocon ,  Jun Zeng

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L31/062

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

    摘要： An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

    摘要翻译： 改进的沟槽MOS门控器件包括单晶半导体衬底，其上配置有掺杂的上层。 上层在上表面包括具有第一极性的多个重掺杂体区域，并且覆盖在漏极区域上。 上层还在其上表面包括具有与身体区域相反的第二极性的多个重掺杂源区。 栅极沟槽从上层的上表面延伸到漏极区，并且将一个源极区域与另一个源区域分离。 沟槽具有包括介电材料层的底板和侧壁，并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。 因此，沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。 用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽被填充到具有导电栅极材料的选定的电平，在其上形成隔离电介质层，其上表面与上层的上表面基本共面 的设备。