公开(公告)号：US20050145934A1

公开(公告)日：2005-07-07

申请号：US11052258

申请日：2005-02-07

申请人： Christopher Kocon ,  Alan Elbanhawy

发明人： Christopher Kocon ,  Alan Elbanhawy

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7813

摘要： A method for reducing miller capacitance and switching losses in an integrated circuit includes providing a switching gate electrode having respective portions that are coplanar with the source and well regions of the integrated circuit. The switching gate electrode is configured for switching the integrated circuit on and off in response to a relatively small change in applied voltage. A shielding gate electrode is formed with respective portions coplanar with the switching electrode and the well region. The shielding electrode is configured for charging the gate-to-drain overlap region of the integrated circuit.

摘要翻译： 一种用于降低集成电路中的磨机电容和开关损耗的方法包括提供具有与集成电路的源区和阱区共面的各部分的开关栅电极。 开关栅电极被配置为响应于施加电压的相对较小的变化而导通和关断集成电路。 屏蔽栅极形成有与开关电极和阱区共面的各个部分。 屏蔽电极被配置为对集成电路的栅极 - 漏极重叠区域进行充电。

公开(公告)号：US20060214222A1

公开(公告)日：2006-09-28

申请号：US11445111

申请日：2006-05-31

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J. Jung ,  H. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J. Jung ,  H. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：US20060214221A1

公开(公告)日：2006-09-28

申请号：US11445020

申请日：2006-05-31

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：US20050167742A1

公开(公告)日：2005-08-04

申请号：US11026276

申请日：2004-12-29

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： G06F1/26 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/68 ,  H01L23/495 ,  H01L23/498 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H02M3/00 ,  H02M3/335

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

摘要翻译： 公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。 本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。 本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。 根据本发明的其它方面提供了改进的功率器件制造方法。 提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。 根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。 本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

公开(公告)号：US20070187781A1

公开(公告)日：2007-08-16

申请号：US11404062

申请日：2006-04-12

申请人： Christopher Kocon

发明人： Christopher Kocon

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/7816 ,  H01L29/7824

摘要： A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

摘要翻译： 半导体功率晶体管包括漂移区中的第一导电类型的漂移区和第二导电类型的阱区，使得阱区和漂移区在它们之间形成pn结。 第一导电类型的第一高度掺杂的硅区域在阱区中，并且第二高度掺杂的硅区域在漂移区域中。 第二高掺杂硅区域与阱区域横向间隔开，使得在将晶体管置于导通状态时，电流通过漂移区域在第一和第二高掺杂硅区域之间横向流动。 延伸到垂直于电流的漂移区域中的多个沟槽中的每一个包括衬在至少一部分沟槽侧壁和至少一个导电电极的电介质层。

公开(公告)号：US20060011962A1

公开(公告)日：2006-01-19

申请号：US11140249

申请日：2005-05-26

申请人： Christopher Kocon

发明人： Christopher Kocon

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L29/7804 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/7838 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01078 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00

摘要： An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity type. The transistor further includes a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the conduction region and the channel regions. A number of charge balancing structures are integrated with the semiconductor region so as to extend parallel to the current flow. In a blocking state, the charge balancing structures influence an electric field in the conduction region so as to increase the blocking capability of the accumulation-mode field effect transistor.

摘要翻译： 累积模式场效应晶体管包括多个栅极和具有与多个栅极中的每一个相邻但绝缘的沟道区的半导体区域。 半导体区域还包括导电区域，其中沟道区域和导电区域是第一导电类型。 晶体管还包括漏极端子和源极端子，其被配置为使得当累积模式场效应晶体管处于导通状态时，电流通过导电区域和沟道区域从漏极端子流到源极端子。 多个电荷平衡结构与半导体区域集成，以便平行于电流流动延伸。 在阻塞状态下，电荷平衡结构影响导电区域中的电场，从而增加积累型场效应晶体管的阻挡能力。

公开(公告)号：US20070138548A1

公开(公告)日：2007-06-21

申请号：US11676613

申请日：2007-02-20

申请人： Christopher Kocon ,  Shuming Xu ,  Jacek Korec

发明人： Christopher Kocon ,  Shuming Xu ,  Jacek Korec

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823

摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

摘要翻译： 横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。 在半导体层中形成第一导电类型的源极区域和漏极延伸区域。 在半导体层中形成第二导电类型的体区。 导电栅极形成在沟道区域上形成的栅极电介质层上。 漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。 漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。 源极触点将源极区域电连接到主体区域。

公开(公告)号：US20060076617A1

公开(公告)日：2006-04-13

申请号：US10962367

申请日：2004-10-08

申请人： Praveen Shenoy ,  Christopher Kocon

发明人： Praveen Shenoy ,  Christopher Kocon

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

摘要翻译： 在本发明的一个实施例中，沟槽MOS门控晶体管包括形成具有第二导电类型的阱区的pn结的第一导电类型的第一区域。 阱区域具有平坦的底部部分和比平坦的底部部分更深的部分。 栅极沟槽延伸到阱区域中。 通道区域沿着栅极沟槽的外侧壁在阱区域中延伸。 栅极沟槽具有终止于第一区域内的第一底部部分和终止于阱区域较深部分内的第二底部部分，使得当晶体管处于导通状态时，阱区域的较深部分防止电流 从而流过位于井区域较深部分正上方的那些通道区域部分。

公开(公告)号：US20080017920A1

公开(公告)日：2008-01-24

申请号：US11620002

申请日：2007-01-04

申请人： Steven Sapp ,  Ashok Challa ,  Christopher Kocon

发明人： Steven Sapp ,  Ashok Challa ,  Christopher Kocon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/7803

摘要： A field effect transistor is disclosed. In one embodiment, the field effect transistor includes a trench extending into a drift region of the field effect transistor. A shield electrode in a lower portion of the trench is insulated from the drift region by a shield dielectric. A gate electrode in the trench over the shield electrode is insulated from the shield electrode by an inter-electrode dielectric. A source region is formed adjacent the trench. A resistive element is coupled to the shield electrode and to a source region in the field effective transistor.

摘要翻译： 公开了一种场效应晶体管。 在一个实施例中，场效应晶体管包括延伸到场效应晶体管的漂移区的沟槽。 沟槽下部的屏蔽电极通过屏蔽电介质与漂移区绝缘。 屏蔽电极上的沟槽中的栅电极通过电极间绝缘体与屏蔽电极绝缘。 在沟槽附近形成源区。 电阻元件耦合到屏蔽电极和场有效晶体管中的源极区域。

公开(公告)号：US20070264782A1

公开(公告)日：2007-11-15

申请号：US11829262

申请日：2007-07-27

申请人： Praveen Shenoy ,  Christopher Kocon

发明人： Praveen Shenoy ,  Christopher Kocon

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

摘要翻译： 沟槽MOS门控晶体管如下形成。 提供第一导电类型的第一区域。 然后在第一区域的上部形成第二导电类型的阱区域。 形成了延伸穿过阱区并终止于第一区域内的沟槽。 沿着沟槽底部的预定部分注入第二导电类型的掺杂剂，以沿沟槽底部形成与阱区连续的区域，使得当晶体管处于导通状态时，阱区的较深部分 防止电流流过位于阱区域较深部分正上方的那些沟道区域部分。