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    Detection of Broken Word-Lines in Memory Arrays
    5.
    发明申请
    Detection of Broken Word-Lines in Memory Arrays 有权
    在内存数组中检测破碎的字线

    公开(公告)号：US20120008405A1

    公开(公告)日：2012-01-12

    申请号：US12833167

    申请日：2010-07-09

    申请人： Grishma Shailesh Shah ,  Yan Li

    发明人： Grishma Shailesh Shah ,  Yan Li

    IPC分类号： G11C16/04

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/702 ,  G11C2029/1202

    摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.

    摘要翻译： 提供技术和相应的电路用于检测存储器阵列中的断字。 在示例性实施例中，存储器电路的编程操作沿着字线在第一多个存储器单元上执行，其中编程操作包括一系列交替编程脉冲和验证操作，存储器单元分别从 进一步编程脉冲验证。 基于用于第一多个第一子集的第一子集的存储器单元的编程脉冲的数量来确定字线是否有缺陷，以相对于第二子集的第二子集的存储器单元的编程脉冲的数量进行编程 第一多个以验证编程，其中第一和第二子集各自包含多个存储器单元并且不相同。

    Detection of broken word-lines in memory arrays
    6.
    发明授权
    Detection of broken word-lines in memory arrays 有权
    检测存储器阵列中断字符

    公开(公告)号：US08305807B2

    公开(公告)日：2012-11-06

    申请号：US12833167

    申请日：2010-07-09

    申请人： Grishma Shailesh Shah ,  Yan Li

    发明人： Grishma Shailesh Shah ,  Yan Li

    IPC分类号： G11C16/34

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/702 ,  G11C2029/1202

    摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.

    摘要翻译： 提供技术和相应的电路用于检测存储器阵列中的断字。 在示例性实施例中，存储器电路的编程操作沿着字线在第一多个存储器单元上执行，其中编程操作包括一系列交替编程脉冲和验证操作，存储器单元分别从 进一步编程脉冲验证。 基于用于第一多个第一子集的第一子集的存储器单元的编程脉冲的数量来确定字线是否有缺陷，以相对于第二子集的第二子集的存储器单元的编程脉冲的数量进行编程 第一多个以验证编程，其中第一和第二子集各自包含多个存储器单元并且不相同。