Abstract:
A planar illumination device includes at least one light source, a housing structure, at least one light guide plate, and at least one light exiting surface. The at least one light source is received in the housing structure. The housing structure includes at least one light emitting surface through which the light emitted from the at least one light source exits the at least one housing. The at least one light guide plate includes at least one light incidence surface through which the light enters into the at least one light guide plate, and contacts with the at least one light emitting surface. The light exits the at least one light guide plate through the at least one light exiting surface. The at least one light exiting surface includes a plurality of continuously connected bulge points formed thereon.
Abstract:
A light-emitting panel (50) includes a first light source (511) for emitting first light of a first single color, a second light source (512) for emitting second light of a second single color and a light guide plate (52). The light guide plate (52) includes a light incident surface (55) for receiving the first and second light and a display surface (53). A plurality of first microstructures (561) and second microstructures (562) are formed at the display surface (53). The first and second microstructures (561,562) are configured for allowing the first and second light to exit therethrough. The first and second microstructures (561,562) are respectively arranged to form a first pattern (58) and a second pattern (59). A first dye material and second dye material are respectively applied to the first and second microstructures (561,562).
Abstract:
A light-emitting panel (50) includes a first light source (511) for emitting first light of a first single color, a second light source (512) for emitting second light of a second single color and a light guide plate (52). The light guide plate (52) includes a light incident surface (55) for receiving the first and second light and a display surface (53). A plurality of first microstructures (561) and second microstructures (562) are formed at the display surface (53). The first and second microstructures (561,562) are configured for allowing the first and second light to exit therethrough. The first and second microstructures (561,562) are respectively arranged to form a first pattern (58) and a second pattern (59). A first dye material and second dye material are respectively applied to the first and second microstructures (561,562).
Abstract:
A light source device includes a lead frame, a first solid-state lighting chip, a first transparent encapsulation, a second solid-state lighting chip, and a second transparent encapsulation. The first solid-state lighting chip and the second solid-state lighting chip are respectively located at two opposite sides of the lead frame and electrically connected to the lead frame. The first transparent encapsulation and the second transparent encapsulation respectively encapsulate the first solid-state lighting chip and the second solid-state lighting chip.
Abstract:
A light chain includes a plurality of light emitting diodes (LEDs) electrically connected to each other. Each LED includes an LED chip having a first pole and a second pole, and a packaging layer encapsulating the LED chip. A first electrode has an inner end connected to the first pole, and an outer end extending to the outside of the packaging layer. A second electrode has an inner end connected to the second pole, and an outer end extending to the outside of the packaging layer. A third electrode has a first outer end and a second outer end located at the outside. The outer end of the first electrode and the first outer end cooperatively form a first plug; the outer end of the second electrode and the second outer end cooperatively form a second plug configured to attach to a first plug of an adjacent LED.
Abstract:
The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.
Abstract:
A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer. The first insulating layer is patterned by using the gate as an etching mask so as to expose the metal oxide semiconductor layer to serve as a source region and a drain region. A dielectric layer is formed on the substrate to cover the gate and the oxide semiconductor layer, where the dielectric layer has at least one of hydrogen group and hydroxyl group. A heating treatment is performed so that the at least one of hydrogen group and hydroxyl group reacts with the source region and the drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region respectively are formed on the dielectric layer.
Abstract:
A second-harmonic generation nonlinear frequency converter includes a nonlinear optical crystal. The nonlinear optical crystal includes a plurality of sections. The sections connect to each other in sequence, and each section has a phase different from others. Each of the phases includes a positive domain and a negative domain. Each of the sections includes a plurality of quasi-phase-matching structures. The quasi-phase-matching structures connect to each other in sequence and have the same phase in one section.
Abstract:
A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer. The first insulating layer is patterned by using the gate as an etching mask so as to expose the metal oxide semiconductor layer to serve as a source region and a drain region. A dielectric layer is formed on the substrate to cover the gate and the oxide semiconductor layer, where the dielectric layer has at least one of hydrogen group and hydroxyl group. A heating treatment is performed so that the at least one of hydrogen group and hydroxyl group reacts with the source region and the drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region respectively are formed on the dielectric layer.
Abstract:
An LED lamp includes a heat sink including a base having a heat-dissipating face, an LED module including a printed circuit board mounted on the base and a plurality of LEDs disposed on the printed circuit board, and a connecter electrically connecting the LED module to a power supply. The heat sink further includes a plurality of spiral fins protruding outwardly from the heat-dissipating face of the base.