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公开(公告)号:US10903349B2
公开(公告)日:2021-01-26
申请号:US16413646
申请日:2019-05-16
发明人: Louis Hutin , Sylvain Barraud , Benoit Bertrand , Maud Vinet
IPC分类号: H01L29/06 , H01L29/775 , H01L29/423 , H01L29/66
摘要: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.
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公开(公告)号:US11152360B2
公开(公告)日:2021-10-19
申请号:US16723285
申请日:2019-12-20
IPC分类号: H01L27/092 , H01L21/8238 , H01L29/10 , H01L29/423 , H01L27/06 , H01L21/822
摘要: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.
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公开(公告)号:US20190148367A1
公开(公告)日:2019-05-16
申请号:US16184346
申请日:2018-11-08
IPC分类号: H01L27/06 , H01L21/822 , H01L21/8234
摘要: Production of an integrated circuit provided with several superposed levels of transistors, comprising: providing a structure provided with transistors of a lower level covered by an insulating layer itself covered by a stack with a first doped semi-conducting layer according to a doping of a first type, and a second doped semi-conducting layer according to a doping of opposite type, the first doped semi-conducting layer and the second doped semi-conducting layer being superposed and in contact with one another, etching the stack so as to form, on the insulating layer, a first block and a second block, then, removing in a given zone of the second block, the second given doped semi-conducting layer, forming a first gate on the second doped semi-conducting layer of the first block and a second gate on the first doped semi-conducting layer of the second block.
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4.
公开(公告)号:US10217849B2
公开(公告)日:2019-02-26
申请号:US15837298
申请日:2017-12-11
发明人: Sylvain Barraud , Emmanuel Augendre , Remi Coquand , Shay Reboh
IPC分类号: H01L21/00 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/786
摘要: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
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5.
公开(公告)号:US20210391326A1
公开(公告)日:2021-12-16
申请号:US17461428
申请日:2021-08-30
IPC分类号: H01L27/092 , H01L21/8238 , H01L29/10 , H01L29/423 , H01L27/06 , H01L21/822
摘要: Implementation of a device with stacked transistors comprising:
a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other,
a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.-
公开(公告)号:US11889704B2
公开(公告)日:2024-01-30
申请号:US17132127
申请日:2020-12-23
发明人: Sylvain Barraud , François Andrieu
IPC分类号: H10B63/00 , H01L29/06 , H01L29/423 , H10N70/20 , H01L21/02 , H01L29/66 , H01L29/775 , H01L29/786 , H10N70/00
CPC分类号: H10B63/30 , H01L21/02532 , H01L21/02603 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/775 , H01L29/78696 , H10N70/011 , H10N70/24
摘要: A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.
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公开(公告)号:US11532670B2
公开(公告)日:2022-12-20
申请号:US17130006
申请日:2020-12-22
发明人: Sylvain Barraud , François Andrieu
IPC分类号: H01L27/24 , G11C5/06 , G11C13/00 , H01L21/822 , H01L45/00
摘要: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.
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公开(公告)号:US11239374B2
公开(公告)日:2022-02-01
申请号:US16697558
申请日:2019-11-27
发明人: Sylvain Barraud , Joris Lacord
IPC分类号: H01L29/786 , H01L29/423 , H01L29/66 , H01L29/78
摘要: A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.
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公开(公告)号:US11088259B2
公开(公告)日:2021-08-10
申请号:US16413652
申请日:2019-05-16
发明人: Louis Hutin , Sylvain Barraud , Benoit Bertrand , Maud Vinet
IPC分类号: H01L29/66 , H01L21/3105 , H01L29/40
摘要: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.
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公开(公告)号:US10522669B2
公开(公告)日:2019-12-31
申请号:US15724862
申请日:2017-10-04
发明人: Sylvain Barraud
IPC分类号: H01L29/76 , H01L27/118 , H01L29/12 , H01L29/66 , B82Y10/00 , H01L29/08 , H01L29/167 , H01L21/768 , H01L29/786
摘要: A method of making a quantum device with a quantum island structure is provided. The method includes the formation of a stack including a first semiconducting layer based on an undoped semiconducting material on which at least one second doped semiconducting layer is grown by epitaxy, the doping being made during epitaxial growth, a first region belonging to the first semiconducting layer and a second region belonging to the second semiconducting layer being suitable for forming a quantum island.
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