Electronic component with multiple quantum islands

    公开(公告)号:US10903349B2

    公开(公告)日:2021-01-26

    申请号:US16413646

    申请日:2019-05-16

    摘要: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.

    3D CIRCUIT WITH N AND P JUNCTIONLESS TRANSISTORS

    公开(公告)号:US20190148367A1

    公开(公告)日:2019-05-16

    申请号:US16184346

    申请日:2018-11-08

    摘要: Production of an integrated circuit provided with several superposed levels of transistors, comprising: providing a structure provided with transistors of a lower level covered by an insulating layer itself covered by a stack with a first doped semi-conducting layer according to a doping of a first type, and a second doped semi-conducting layer according to a doping of opposite type, the first doped semi-conducting layer and the second doped semi-conducting layer being superposed and in contact with one another, etching the stack so as to form, on the insulating layer, a first block and a second block, then, removing in a given zone of the second block, the second given doped semi-conducting layer, forming a first gate on the second doped semi-conducting layer of the first block and a second gate on the first doped semi-conducting layer of the second block.

    3D memory and manufacturing process

    公开(公告)号:US11532670B2

    公开(公告)日:2022-12-20

    申请号:US17130006

    申请日:2020-12-22

    摘要: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

    Method of fabricating a field effect transistor

    公开(公告)号:US11239374B2

    公开(公告)日:2022-02-01

    申请号:US16697558

    申请日:2019-11-27

    摘要: A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.

    Method of manufacturing an electronic component including multiple quantum dots

    公开(公告)号:US11088259B2

    公开(公告)日:2021-08-10

    申请号:US16413652

    申请日:2019-05-16

    摘要: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.