Abstract:
Disclosed herein are certain embodiments of a coding system and method that guarantee a pair of sync bits in a transcoded block will appear on the same physical lane. Embodiments may then use this property for data synchronization and to guarantee a bit transition in a certain amount of time on a physical lane. Embodiments of a coding system and process for configuring alignment marker blocks are also disclosed.
Abstract:
High speed communication networks divide data traffic into multiple physical lanes. For example, the IEEE standard 40G/100G supports sending Ethernet frames at 40/100 gigabits per second over multiple 10/25 Gb/s lanes. Techniques are disclosed for aligning the data across the physical lanes.
Abstract:
A marker spacing between two consecutive alignment marker (AM) blocks is defined for virtual lanes in a multi-virtual-lane networking protocol. A system using the networking protocol includes circuitry configured to identify virtual and physical lane groupings and numbers based on the AM blocks. The system may use error coding groups to allow for distribution of the AM blocks to the physical lanes in integer numbers of error correction blocks. The identification scheme may be based on sequences derived from a known bit pattern and the bit inverse of the bit pattern. The system may include matching units identify instances of the bit pattern and its bit inverse.
Abstract:
A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a mother code or a plurality of concatenated daughter codes based on an encoding option. The mother code and the plurality of concatenated daughter codes have a same number of coded data symbols. The mother code includes a first source number of source symbols and a first parity number of parity symbols. The daughter code includes fewer source symbols and fewer parity symbols than the mother code.
Abstract:
Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block.
Abstract:
Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block.
Abstract:
A communication system and a method are provided. The communication system includes an encoder configured to encode source data and output an encoded frame including a mother code or a plurality of concatenated daughter codes based on an encoding option. The mother code and the plurality of concatenated daughter codes have a same number of coded data symbols. The mother code includes a first source number of source symbols and a first parity number of parity symbols. The daughter code includes fewer source symbols and fewer parity symbols than the mother code.
Abstract:
Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.
Abstract:
A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a plurality of rows and a plurality of columns. The plurality of rows include a row component code. The plurality of columns include a column component code. The row component code is configured to achieve a lower bit error rate than the column component code in communication channels having a same signal to noise ratio.
Abstract:
High speed communication networks divide data traffic into multiple physical lanes. For example, the IEEE standard 40 G/100 G supports sending Ethernet frames at 40/100 gigabits per second over multiple 10/25 Gb/s lanes. Techniques are disclosed for aligning the data across the physical lanes.