公开(公告)号：US20170054027A1

公开(公告)日：2017-02-23

申请号：US14831106

申请日：2015-08-20

Applicant: BROADCOM CORPORATION

Inventor： Qing Liu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

Abstract: A wimpy finFET device and method for fabricating the same is described. The device is fabricated by forming a mandrel that is non-perpendicular to long axes of the underlying fin(s) (i.e., the mandrel is formed at a non-quadrantal angle with respect to the long axes). Spacers formed on the sidewalls of the angled mandrel are thus also formed non-perpendicular to the long axes. The spacers are used to pattern underlying layer(s) down to the underlying fin(s) to form the gates for the device. Because the patterned layer(s) are also formed at a non-quadrantal angle, the width of the patterned layer(s) over the underlying fin(s) is greater than would be if the patterned layer(s) were formed at, e.g., a right angle with respect to the long axis. The desired gate length and gate pitch is respectively achieved by determining the angle at which the mandrel is formed and the mandrel width.

Abstract translation: 描述了一种微型finFET器件及其制造方法。 该装置通过形成与下面的翅片的长轴非垂直的心轴（即心轴相对于长轴形成非四角形）而制造。 因此，形成在成角度心轴的侧壁上的间隔物也形成为不垂直于长轴。 间隔件被用于将下面的层向下图案化成下面的翅片以形成装置的门。 由于图案化层也形成为非四面角，所以在下面的翅片之上的图案化层的宽度大于如果图案化层形成在（例如） 相对于长轴为直角。 所需的栅极长度和栅极间距分别通过确定心轴形成的角度和心轴宽度来实现。

公开(公告)号：US20170373074A1

公开(公告)日：2017-12-28

申请号：US15208418

申请日：2016-07-12

Applicant: BROADCOM CORPORATION

Inventor： Qing Liu ,  Akira Ito

IPC: H01L27/112 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L23/528 ,  H01L23/525 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L27/11206 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/517 ,  H01L29/7848

Abstract: A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

公开(公告)号：US20180122942A1

公开(公告)日：2018-05-03

申请号：US15383592

申请日：2016-12-19

Applicant: Broadcom Corporation

Inventor： Shom PONOTH ,  Akira Ito ,  Qing Liu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1095

Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

公开(公告)号：US09583581B1

公开(公告)日：2017-02-28

申请号：US14928222

申请日：2015-10-30

Applicant: Broadcom Corporation

Inventor： Qing Liu

IPC: H01L29/41 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/41783 ,  H01L21/76897 ,  H01L27/088 ,  H01L29/0649

Abstract: An integrated circuit is described as having one or more contact regions to provide one or more interconnections between one or more transistors of the integrated circuit and another integrated circuit. The one or more contact regions represent a self-aligned contact (SAC) whose positioning is determined through one or more patterning processes of a semiconductor fabrication process. The one or more contact regions include one or more contact discontinuities to allow the integrated circuit to accommodate for a wide range of the manufacturing variations and/or the misalignment tolerances by preventing the one or more contact regions from physically contacting other regions, such as gate regions to provide an example, of the one or more transistors. As such, the one or more contact discontinuities have a dynamic size, such as a dynamic area to provide an example, which is dependent upon the manufacturing variations and/or the misalignment tolerances.

Abstract translation: 集成电路被描述为具有一个或多个接触区域以在集成电路的一个或多个晶体管和另一个集成电路之间提供一个或多个互连。 一个或多个接触区域表示通过半导体制造工艺的一个或多个图案化工艺确定其定位的自对准接触（SAC）。 一个或多个接触区域包括一个或多个接触不连续性，以允许集成电路通过防止一个或多个接触区域物理接触其它区域（例如栅极）而适应宽范围的制造变化和/或不对准公差 区域以提供一个或多个晶体管的示例。 因此，一个或多个接触不连续性具有动态尺寸，例如动态区域以提供取决于制造变化和/或不对准公差的示例。

公开(公告)号：US20160351710A1

公开(公告)日：2016-12-01

申请号：US14755625

申请日：2015-06-30

Applicant: Broadcom Corporation

Inventor： Qing Liu ,  Shom Ponoth

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L23/535

CPC classification number: H01L29/41783 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/20 ,  H01L29/78624

Abstract: A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source/drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.

Abstract translation: 三维单片LDMOS晶体管实现垂直设置在包括晶体管的漏极连接的结构的电平之上的漏极结构。 将漏极结构垂直放置在栅极和源极/漏极连接的平面或电平之外，为晶体管产生三维结构。 一个结果是晶体管在基板上消耗远小的横向面积。 横向面积的减少又提供了诸如允许晶体管更密集地布置在衬底上并且允许在衬底上形成其他类型的附加器件的优点。