公开(公告)号：US09312389B2

公开(公告)日：2016-04-12

申请号：US14529869

申请日：2014-10-31

Applicant: Broadcom Corporation

Inventor： Shom Ponoth ,  Hemant Vinayak Deshpande

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7851 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7853

Abstract: Systems and methods are provide to achieve undoped body bulk silicon based devices, such as field effect transistors (FETS) and Fin Field Effect Transistors (FinFETs). In an embodiment, an epitaxial growth technique is used to form the silicon of an active region of a fin of a FinFET once a punchthrough stop (PTS) layer has been formed. In an embodiment, the epitaxial growth technique according to embodiments of the present disclosure produces a fin with a small notch in the active region.

Abstract translation: 提供系统和方法来实现非掺杂体体硅基器件，例如场效应晶体管（FETS）和Fin场效应晶体管（FinFET）。 在一个实施例中，一旦形成穿通停止（PTS）层，就使用外延生长技术来形成FinFET的鳍的有源区的硅。 在一个实施例中，根据本公开实施例的外延生长技术在有源区域中产生具有小凹口的翅片。

公开(公告)号：US20150340502A1

公开(公告)日：2015-11-26

申请号：US14529869

申请日：2014-10-31

Applicant: Broadcom Corporation

Inventor： Shom Ponoth ,  Hemant Vinayak Deshpande

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7853

Abstract: Systems and methods are provide to achieve undoped body bulk silicon based devices, such as field effect transistors (FETS) and Fin Field Effect Transistors (FinFETs). In an embodiment, an epitaxial growth technique is used to form the silicon of an active region of a fin of a FinFET once a punchthrough stop (PTS) layer has been formed. In an embodiment, the epitaxial growth technique according to embodiments of the present disclosure produces a fin with a small notch in the active region.

Abstract translation: 提供系统和方法来实现非掺杂体体硅基器件，例如场效应晶体管（FETS）和Fin场效应晶体管（FinFET）。 在一个实施例中，一旦形成穿通停止（PTS）层，就使用外延生长技术来形成FinFET的鳍的有源区的硅。 在一个实施例中，根据本公开实施例的外延生长技术在有源区域中产生具有小凹口的翅片。

公开(公告)号：US09583613B2

公开(公告)日：2017-02-28

申请号：US14625047

申请日：2015-02-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Shom Ponoth

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7824 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/78624

Abstract: A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.

Abstract translation: 半导体器件包括设置在半导体衬底中的第一阱。 半导体器件还包括设置在半导体衬底中的第二阱。 半导体器件还包括在源极区域和漏极区域之间的源极区域，漏极区域和栅极结构。 栅极结构设置在第一阱的上方。 源极区包括在第一阱上方的第一导电接触。 漏极区域包括在第二阱上方的第二导电接触，漏极区域至少部分地通过第一外延区域与第二阱连接。 第一外延区域和第二阱被配置为将施加在源极区域和漏极区域上的第一驱动电压降低到施加在栅极结构上的第二电压。

公开(公告)号：US20160351710A1

公开(公告)日：2016-12-01

申请号：US14755625

申请日：2015-06-30

Applicant: Broadcom Corporation

Inventor： Qing Liu ,  Shom Ponoth

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L23/535

CPC classification number: H01L29/41783 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/20 ,  H01L29/78624

Abstract: A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source/drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.

Abstract translation: 三维单片LDMOS晶体管实现垂直设置在包括晶体管的漏极连接的结构的电平之上的漏极结构。 将漏极结构垂直放置在栅极和源极/漏极连接的平面或电平之外，为晶体管产生三维结构。 一个结果是晶体管在基板上消耗远小的横向面积。 横向面积的减少又提供了诸如允许晶体管更密集地布置在衬底上并且允许在衬底上形成其他类型的附加器件的优点。

公开(公告)号：US20160211367A1

公开(公告)日：2016-07-21

申请号：US14625047

申请日：2015-02-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Shom Ponoth

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/78624

Abstract: A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.

Abstract translation: 半导体器件包括设置在半导体衬底中的第一阱。 半导体器件还包括设置在半导体衬底中的第二阱。 半导体器件还包括在源极区域和漏极区域之间的源极区域，漏极区域和栅极结构。 栅极结构设置在第一阱的上方。 源极区包括在第一阱上方的第一导电接触。 漏极区域包括在第二阱上方的第二导电接触，漏极区域至少部分地通过第一外延区域与第二阱连接。 第一外延区域和第二阱被配置为将施加在源极区域和漏极区域上的第一驱动电压降低到施加在栅极结构上的第二电压。