公开(公告)号：US08102705B2

公开(公告)日：2012-01-24

申请号：US12635449

申请日：2009-12-10

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 这些技术还允许在控制器上用纠错码（ECC）对数据进行编码，该错误校正码在将数据传送到存储器以二进制形式写入之前考虑其最终的多状态存储。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US08228729B2

公开(公告)日：2012-07-24

申请号：US13333494

申请日：2011-12-21

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US20120113716A1

公开(公告)日：2012-05-10

申请号：US13333494

申请日：2011-12-21

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US20100309720A1

公开(公告)日：2010-12-09

申请号：US12635449

申请日：2009-12-10

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 这些技术进一步允许在控制器上用纠错码（ECC）编码数据，该数据在将数据传送到存储器以二进制形式写入之前考虑到其最终的多状态存储。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US08681548B2

公开(公告)日：2014-03-25

申请号：US13463422

申请日：2012-05-03

申请人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

发明人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

摘要： In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

摘要翻译： 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组成5个部分，并且用户数据可以被连续地从一个部门写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑，以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。

公开(公告)号：US20130294162A1

公开(公告)日：2013-11-07

申请号：US13463422

申请日：2012-05-03

申请人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

发明人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

摘要： In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

摘要翻译： 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组成5个部分，并且用户数据可以被连续地从一个部门写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑，以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。

公开(公告)号：USD910193S1

公开(公告)日：2021-02-09

申请号：US29686746

申请日：2019-04-08

申请人： Bo Liu

设计人： Bo Liu

公开(公告)号：US09796022B2

公开(公告)日：2017-10-24

申请号：US13587450

申请日：2012-08-16

申请人： Shengen Zhang ,  Bo Liu ,  Jianjun Tian ,  Dean Pan ,  Bin Li

发明人： Shengen Zhang ,  Bo Liu ,  Jianjun Tian ,  Dean Pan ,  Bin Li

IPC分类号： B22F9/00 ,  B22F3/23 ,  B22F5/10 ,  B22F7/08 ,  B22F8/00

CPC分类号： B22F9/00 ,  B22F3/23 ,  B22F5/106 ,  B22F7/08 ,  B22F8/00 ,  Y02P10/24 ,  Y02W30/541

摘要： The invention provides a pollution-free reuse method for iron-based grinding waste, involving the technology of recycling economy, with special reference to the metallurgical industry, iron-based grinding waste green recycling technology. The present invention of the iron grinding waste recycling and reuse methods includes degreasing, heat treatment, sieving, matching, and obtains iron-based alloyed powders, which can be used in SHS lined steel pipe, powder metallurgy structural component, magnetic grinding, thermal spray. More than 95% iron-based alloyed powders can be recycled from wide source of iron-based grinding waste. The invention has the advantage of low cost, no secondary pollution and wide application.

公开(公告)号：US09580644B2

公开(公告)日：2017-02-28

申请号：US13142285

申请日：2009-12-22

申请人： Gongming Wei ,  Yadong Liu ,  Henk van Houten ,  Bo Liu ,  Hugo Johan Cornelissen ,  Xiaoyan Zhu ,  Cornelis Reinder Ronda ,  Hendrikus albertus adrianus maria de Ruijter

发明人： Gongming Wei ,  Yadong Liu ,  Henk van Houten ,  Bo Liu ,  Hugo Johan Cornelissen ,  Xiaoyan Zhu ,  Cornelis Reinder Ronda ,  Hendrikus albertus adrianus maria de Ruijter

IPC分类号： F21V8/00 ,  C09K11/06 ,  F21W131/30 ,  F21Y101/00

CPC分类号： C09K11/06 ,  F21W2131/3005 ,  F21Y2101/00 ,  F21Y2115/10 ,  G02B6/0035 ,  G02B6/0068

摘要： To improve the illumination efficiency of hand-held illumination devices, this invention proposes a new illumination device having the “rolling” function, which is capable of illuminating the target area on which a user is currently focusing and rolling the illuminated area as the user is reading forward or backward. The illumination device comprises two pluralities of lighting elements, an illuminating body and a controller. The controller can control one plurality of lighting elements to emit light to illuminate a part of the illuminating body, which can further deflect the light to a part of the surface of the target.

摘要翻译： 为了提高手持式照明装置的照明效率，本发明提出了一种具有“滚动”功能的新的照明装置，其能够照射用户正在聚焦的目标区域，并且在使用者是照明区域时滚动照明区域 向前或向后读。 照明装置包括两个照明元件，照明体和控制器。 控制器可以控制多个照明元件发光以照亮照明体的一部分，这可以进一步将光偏转到目标表面的一部分。

公开(公告)号：US09214644B2

公开(公告)日：2015-12-15

申请号：US13519176

申请日：2011-12-07

申请人： Andrew Gabriel Rinzler ,  Mitchell Austin McCarthy ,  Bo Liu

发明人： Andrew Gabriel Rinzler ,  Mitchell Austin McCarthy ,  Bo Liu

IPC分类号： H01L51/52 ,  H01L29/16 ,  H01L29/78 ,  H01L51/05 ,  H01L51/10 ,  H01L27/32 ,  B82Y99/00 ,  H01L51/00

CPC分类号： H01L51/5203 ,  B82Y99/00 ,  H01L27/3262 ,  H01L27/3274 ,  H01L29/1606 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/102 ,  H01L51/5296

摘要： Various embodiments are provided for dilute source enabled vertical organic light emitting transistors. In various embodiments, a display panel includes an array of pixels. In one embodiment, among others, at least one pixel includes a switching transistor and a driving transistor coupled to the switching transistor, where the driving transistor is configured to emit light responsive to activation by the switching transistor. The driving transistor may be a dilute source enabled vertical organic light emitting transistor (DS-VOLET). The switching transistor may include a dilute source enabled vertical-field effect transistor (DS-VFET). In another embodiment, a double dilute source enabled vertical-field effect transistor (DS-VFET) includes a first DS-VFET coupled to a second DS-VFET.

摘要翻译： 提供了用于稀释源的垂直有机发光晶体管的各种实施例。 在各种实施例中，显示面板包括像素阵列。 在一个实施例中，至少一个像素包括开关晶体管和耦合到开关晶体管的驱动晶体管，其中驱动晶体管被配置为响应于开关晶体管的激活而发光。 驱动晶体管可以是具有稀释源的垂直有机发光晶体管（DS-VOLET）。 开关晶体管可以包括具有稀释源的垂直场效应晶体管（DS-VFET）。 在另一个实施例中，双稀释源使能的垂直场效应晶体管（DS-VFET）包括耦合到第二DS-VFET的第一DS-VFET。