公开(公告)号：US20100309720A1

公开(公告)日：2010-12-09

申请号：US12635449

申请日：2009-12-10

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 这些技术进一步允许在控制器上用纠错码（ECC）编码数据，该数据在将数据传送到存储器以二进制形式写入之前考虑到其最终的多状态存储。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US08228729B2

公开(公告)日：2012-07-24

申请号：US13333494

申请日：2011-12-21

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US20120113716A1

公开(公告)日：2012-05-10

申请号：US13333494

申请日：2011-12-21

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US08102705B2

公开(公告)日：2012-01-24

申请号：US12635449

申请日：2009-12-10

申请人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

发明人： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

摘要翻译： 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 这些技术还允许在控制器上用纠错码（ECC）对数据进行编码，该错误校正码在将数据传送到存储器以二进制形式写入之前考虑其最终的多状态存储。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US20110002169A1

公开(公告)日：2011-01-06

申请号：US12498220

申请日：2009-07-06

申请人： Yan Li ,  Kwang-ho Kim ,  Frank W. Tsai ,  Aldo Bottelli

发明人： Yan Li ,  Kwang-ho Kim ,  Frank W. Tsai ,  Aldo Bottelli

IPC分类号： G11C16/06 ,  G11C29/00 ,  G11C7/10 ,  G11C16/04

CPC分类号： G11C29/00 ,  G11C16/10 ,  G11C29/808

摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.

摘要翻译： 介绍了基于列的缺陷管理技术。 存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理 作为缺陷，或者列的单个位是否有缺陷。 然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。 当列是坏的但是仅在位电平时，好的位仍然可以用于数据，尽管这可以在对于某些位的编程的惩罚下完成，如下面进一步描述的。 还描述了通过一组列测试来构建的用于收集位信息的自建内置自检（BIST）流程。 基于该信息，可以通过控制器或存储器提取坏位并将其重新分组为字节，以更有效地使用列冗余区域。

公开(公告)号：US08630120B2

公开(公告)日：2014-01-14

申请号：US13277915

申请日：2011-10-20

申请人： Min She ,  Yan Li ,  Kwang-Ho Kim ,  Siu Lung Chan

发明人： Min She ,  Yan Li ,  Kwang-Ho Kim ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/06 ,  G11C16/3418

摘要： A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.

摘要翻译： 提出了一种紧凑且通用的感应放大器。 在其他功能中，这种感测放大器布置提供了一种在进行数据扫描时对位线进行预充电的方法。 另一个特征是，感测放大器电路可以提供一种使用动态锁存器来设置快速写入（QPW）技术中使用的三个不同位线电平的方法，其中快速写入是一种技术，其中沿着给定字线的单元格被选择用于编程 可以启用，禁止或部分禁止编程。 此外，它可以提供一种方便的方式来测量电池电流。

公开(公告)号：US20130100740A1

公开(公告)日：2013-04-25

申请号：US13277966

申请日：2011-10-20

申请人： Min She ,  Yan Li ,  Kwang-Ho Kim ,  Siu Lung Chan

发明人： Min She ,  Yan Li ,  Kwang-Ho Kim ,  Siu Lung Chan

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/26 ,  G11C16/28

摘要： A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.

摘要翻译： 提出了一种紧凑且通用的感应放大器。 在其他功能中，这种感测放大器布置提供了一种在进行数据扫描时对位线进行预充电的方法。 另一个特征是，感测放大器电路可以提供一种使用动态锁存器来设置快速写入（QPW）技术中使用的三个不同位线电平的方法，其中快速写入是一种技术，其中沿着给定字线的单元格被选择用于编程 可以启用，禁止或部分禁止编程。 此外，它可以提供一种方便的方式来测量电池电流。

公开(公告)号：US08711625B2

公开(公告)日：2014-04-29

申请号：US13293494

申请日：2011-11-10

申请人： Yan Li ,  Kwang-Ho Kim ,  Frank W. Tsai ,  Aldo Bottelli

发明人： Yan Li ,  Kwang-Ho Kim ,  Frank W. Tsai ,  Aldo Bottelli

IPC分类号： G11C16/06

CPC分类号： G11C29/00 ,  G11C16/10 ,  G11C29/808

摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.

摘要翻译： 介绍了基于列的缺陷管理技术。 存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示该列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示该列是作为一个整体进行处理 作为缺陷，或者列的单个位是否有缺陷。 然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。 当列是坏的，但是仅在位级别，好的位仍然可以用于数据。

公开(公告)号：US08705293B2

公开(公告)日：2014-04-22

申请号：US13277966

申请日：2011-10-20

申请人： Min She ,  Yan Li ,  Kwang-Ho Kim ,  Siu Lung Chan

发明人： Min She ,  Yan Li ,  Kwang-Ho Kim ,  Siu Lung Chan

IPC分类号： G11C7/10

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/26 ,  G11C16/28

摘要： A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.

摘要翻译： 提出了一种紧凑且通用的感应放大器。 在其他功能中，这种感测放大器布置提供了一种在进行数据扫描时对位线进行预充电的方法。 另一个特征是，感测放大器电路可以提供一种使用动态锁存器来设置快速写入（QPW）技术中使用的三个不同位线电平的方法，其中快速写入是一种技术，其中沿着给定字线的单元格被选择用于编程 可以启用，禁止或部分禁止编程。 此外，它可以提供一种方便的方式来测量电池电流。

公开(公告)号：US20120297245A1

公开(公告)日：2012-11-22

申请号：US13293494

申请日：2011-11-10

申请人： Yan Li ,  Kwang-ho Kim ,  Frank W. Tsai ,  Aldo Bottelli

发明人： Yan Li ,  Kwang-ho Kim ,  Frank W. Tsai ,  Aldo Bottelli

IPC分类号： G06F11/07 ,  H03M13/05

CPC分类号： G11C29/00 ,  G11C16/10 ,  G11C29/808

摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.

摘要翻译： 介绍了基于列的缺陷管理技术。 存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理 作为缺陷，或者列的单个位是否有缺陷。 然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。 当列是坏的，但是仅在位级别，好的位仍然可以用于数据。