公开(公告)号：US08971118B2

公开(公告)日：2015-03-03

申请号：US14164712

申请日：2014-01-27

Applicant: Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

Inventor： Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

IPC: G11C16/04 ,  G11C16/06 ,  H01L21/28 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76802 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract translation: 基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。 多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

公开(公告)号：US09373633B2

公开(公告)日：2016-06-21

申请号：US14603827

申请日：2015-01-23

Applicant: Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

Inventor： Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

IPC: H01L21/44 ,  H01L27/115 ,  H01L21/768 ,  H01L21/28 ,  H01L21/308

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76802 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

公开(公告)号：US20090310415A1

公开(公告)日：2009-12-17

申请号：US12480399

申请日：2009-06-08

Applicant: Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

Inventor： Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

IPC: G11C16/04 ,  H01L21/302

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76802 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract translation: 基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。 多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

公开(公告)号：US20150140813A1

公开(公告)日：2015-05-21

申请号：US14603827

申请日：2015-01-23

Applicant: Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

Inventor： Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

IPC: H01L27/115 ,  H01L21/308

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76802 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract translation: 基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。 多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

公开(公告)号：US08325527B2

公开(公告)日：2012-12-04

申请号：US12480399

申请日：2009-06-08

Applicant: Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

Inventor： Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76802 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract translation: 基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。 多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

公开(公告)号：US20140141610A1

公开(公告)日：2014-05-22

申请号：US14164712

申请日：2014-01-27

Applicant: Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

Inventor： Beom-jun Jin ,  Byung-seo Kim ,  Sung-Dong Kim

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76802 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract translation: 基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。 多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

公开(公告)号：US20090273076A1

公开(公告)日：2009-11-05

申请号：US12385731

申请日：2009-04-17

Applicant: Kyong-sei CHOI ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyong-sei CHOI ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01L23/498 ,  H01L23/36

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20110143625A1

公开(公告)日：2011-06-16

申请号：US13033307

申请日：2011-02-23

Applicant: Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01J9/00

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US07915727B2

公开(公告)日：2011-03-29

申请号：US12385731

申请日：2009-04-17

Applicant: Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01L23/498 ,  H01L23/36

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US07453716B2

公开(公告)日：2008-11-18

申请号：US11238381

申请日：2005-09-29

Applicant: Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

Inventor： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC: G11C11/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

Abstract translation: 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。