公开(公告)号：US20240255700A1

公开(公告)日：2024-08-01

申请号：US18102927

申请日：2023-01-30

Applicant: Applied Materials, Inc.

Inventor： Eric Jay Simmons ,  Qintao Zhang ,  Wei Zou ,  Andrew Michael Waite ,  Jared Forrest Traynor ,  Miguel Sam Fung ,  Vincent V. Granuzzo ,  David J. Lee

IPC: G02B6/134 ,  H01L27/144

CPC classification number: G02B6/1347 ,  H01L27/1443

Abstract: Disclosed herein are approaches for forming a uniform film with reduced surface roughness for photonic applications. One method includes providing a workpiece including a contact etch stop layer (CESL) over a device layer, patterning the CESL to expose an upper surface of the device layer in a waveguide target area, and patterning a waveguide from a dielectric film formed over the waveguide target area. The method may further include directing ions into an upper surface of the waveguide using a high-temperature ion implant to decrease a surface roughness of the upper surface of the waveguide.

公开(公告)号：US20220068715A1

公开(公告)日：2022-03-03

申请号：US17006428

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite ,  Johannes M. van Meer ,  Jae Young Lee

IPC: H01L21/8234 ,  H01L21/26

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

公开(公告)号：US11424164B2

公开(公告)日：2022-08-23

申请号：US17006428

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite ,  Johannes M. van Meer ,  Jae Young Lee

IPC: H01L21/8234 ,  H01L21/26

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

公开(公告)号：US20240203743A1

公开(公告)日：2024-06-20

申请号：US18084670

申请日：2022-12-20

Applicant: Applied Materials, Inc.

Inventor： Supakit Charnvanichborikarn ,  Cao-Minh Vincent Lu ,  Ana Cristina Gomez Herrero ,  Hans-Joachim Ludwig Gossmann ,  Wei Zou ,  Andrew Michael Waite

IPC: H01L21/302 ,  C23C14/04 ,  C23C14/48 ,  H01J37/304 ,  H01J37/317 ,  H01L21/02 ,  H01L21/266 ,  H01L21/311

CPC classification number: H01L21/302 ,  C23C14/042 ,  C23C14/48 ,  H01J37/304 ,  H01J37/3171 ,  H01L21/0223 ,  H01L21/266 ,  H01L21/31111

Abstract: A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

公开(公告)号：US11640987B2

公开(公告)日：2023-05-02

申请号：US17167892

申请日：2021-02-04

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/265

Abstract: Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.

公开(公告)号：US20220246746A1

公开(公告)日：2022-08-04

申请号：US17167892

申请日：2021-02-04

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/311

Abstract: Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.