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公开(公告)号：US20190013051A1
公开(公告)日：2019-01-10
申请号：US16129252
申请日：2018-09-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Nuwan S. Jayasena , Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Lisa R. Hsu
CPC classification number: G11C5/06 , G06F12/02 , G06F12/10 , G06F13/1694 , G11C7/1006
Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.
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公开(公告)号：US20150039833A1
公开(公告)日：2015-02-05
申请号：US13957105
申请日：2013-08-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Kai K. Chang , Yasuko Eckert , Gabriel H. Loh , Lisa R. Hsu
CPC classification number: G06F12/0848 , G06F12/122 , Y02D10/13
Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.
Abstract translation: 一种用于在高速缓冲存储器中有效地降低存储器的电力以降低功耗的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，每个存储体包括多个缓存集。 响应于对高速缓存阵列中的多个存储体的第一存储体断电的请求，高速缓存控制器在第一存储体中选择给定类型的高速缓存行，并且确定所选高速缓存行的各个参考位置是否超过 阈。 如果超过阈值，则将所选择的高速缓存行迁移到高速缓存阵列中的第二组。 如果不超过阈值，则将所选的高速缓存行写回低级存储器。
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公开(公告)号：US11301256B2
公开(公告)日：2022-04-12
申请号：US14466080
申请日：2014-08-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Lisa R. Hsu , James Michael O'Connor
Abstract: Embodiments disclose a system and method for reducing virtual address translation latency in a wide execution engine that implements virtual memory. One example method describes a method comprising receiving a wavefront, classifying the wavefront into a subset based on classification criteria selected to reduce virtual address translation latency associated with a memory support structure, and scheduling the wavefront for processing based on the classifying.
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公开(公告)号：US20150293845A1
公开(公告)日：2015-10-15
申请号：US14250474
申请日：2014-04-11
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Lisa R. Hsu , James M. O'Connor , Vilas K. Sridharan , Gabriel H. Loh , Nuwan S. Jayasena , Bradford M. Beckmann
CPC classification number: G06F12/0811 , G06F12/1009 , G06F2212/283 , G06F2212/651
Abstract: Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level. In some embodiments, the memory architecture is visible to the software stack to optimize memory utilization.
Abstract translation: 描述了用于多级存储器层次结构的系统和方法。 每个级别都是基于不同的属性，包括功率，容量，带宽，可靠性和波动性。 在一些实施例中，存储器层级的不同级别可以使用片上堆叠的动态随机存取存储器（提供对数据的快速，高带宽，低能量访问）和片外非易失性随机存取存储器， （提供低功耗，大容量存储），以提供更高容量，更低功耗和更高带宽的性能。 多级存储器可以向处理器呈现统一的接口，从而隐藏特定的存储器硬件和软件实现细节。 多级存储器能够实现满足多个冲突约束的单级存储器的错觉。 比较器从处理器接收存储器地址，处理地址并读取或写入适当的存储器级别。 在一些实施例中，存储器架构对于软件堆栈是可见的以优化存储器利用。
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公开(公告)号：US20140181458A1
公开(公告)日：2014-06-26
申请号：US13726143
申请日：2012-12-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
IPC: G06F12/10
CPC classification number: G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
Abstract translation: 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160062803A1
公开(公告)日：2016-03-03
申请号：US14935056
申请日：2015-11-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Bradford M. Beckmann , Mithuna S. Thottethodi , James M. O'Connor , Mauricio Breternitz , Lisa R. Hsu , Gabriel H. Loh , Yasuko Eckert
CPC classification number: G06F9/5016 , G06F9/5011 , G06F12/0875 , G06F2212/45
Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.
Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制在从一组表中选择的表中执行查找以从资源集合中识别资源。 当资源不可用于执行操作并且直到选择用于执行操作的另一资源为止时，选择机制识别表中的下一个资源，并且当下一个资源可用于执行操作时选择用于执行操作的下一个资源 。
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7.发明授权公开(公告)号：US09244629B2
公开(公告)日：2016-01-26
申请号：US13926765
申请日：2013-06-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Lisa R. Hsu , Gabriel H. Loh , James Michael O'Connor , Nuwan S. Jayasena
CPC classification number: G06F3/067 , G06F9/4881 , G06F9/5033 , G06F12/1036 , G06F2212/302
Abstract: Methods, systems and computer readable storage mediums for more efficient and flexible scheduling of tasks on an asymmetric processing system having at least one host processor and one or more slave processors, are disclosed. An example embodiment includes, determining a data access requirement of a task, comparing the data access requirement to respective local memories of the one or more slave processors selecting a slave processor from the one or more slave processors based upon the comparing, and running the task on the selected slave processor.
Abstract translation: 公开了用于在具有至少一个主处理器和一个或多个从属处理器的非对称处理系统上更有效和灵活地调度任务的方法，系统和计算机可读存储介质。 一个示例实施例包括：确定任务的数据访问需求，将数据访问要求与一个或多个从属处理器的相应本地存储器进行比较，所述一个或多个从属处理器基于比较而从一个或多个从属处理器中选择从属处理器，并且执行任务 在所选的从属处理器上。
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8.发明授权Write endurance management techniques in the logic layer of a stacked memory 有权在堆叠式存储器的逻辑层中写入耐力管理技术公开(公告)号：US09235528B2
公开(公告)日：2016-01-12
申请号：US13725305
申请日：2012-12-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Lisa R. Hsu , Gabriel H. Loh , Michael Ignatowski , Michael J. Schulte , Nuwan S. Jayasena , James M. O'Connor
CPC classification number: G06F12/10 , G06F11/1666 , G06F11/2094
Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.
Abstract translation: 提供体现本发明的一些方面的用于重新映射外部存储器地址和堆叠存储器中的内部存储器位置的系统，方法和存储器件。 堆叠的存储器包括被配置为存储数据的一个或多个存储器层。 堆叠的存储器还包括连接到存储器层的逻辑层。 逻辑层具有被配置为从外部设备接收读取和写入命令的输入/输出（I / O）端口，被配置为保持外部存储器地址和内部存储器位置之间的关联的存储器映射以及耦合到I / O端口，内存映射和内存层，配置为将从外部设备接收的数据存储到内部存储器位置。
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9.发明授权公开(公告)号：US09183055B2
公开(公告)日：2015-11-10
申请号：US13761985
申请日：2013-02-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Bradford M. Beckmann , Mithuna S. Thottethodi , James M. O'Connor , Mauricio Breternitz , Lisa R. Hsu , Gabriel H. Loh , Yasuko Eckert
CPC classification number: G06F9/5016 , G06F9/5011 , G06F12/0875 , G06F2212/45
Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.
Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。
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10.发明申请公开(公告)号：US20140380003A1
公开(公告)日：2014-12-25
申请号：US13926765
申请日：2013-06-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Lisa R. Hsu , Gabriel H. Loh , James Michael O'Connor , Nuwan S. Jayasena
CPC classification number: G06F3/067 , G06F9/4881 , G06F9/5033 , G06F12/1036 , G06F2212/302
Abstract: Methods, systems and computer readable storage mediums for more efficient and flexible scheduling of tasks on an asymmetric processing system having at least one host processor and one or more slave processors, are disclosed. An example embodiment includes, determining a data access requirement of a task, comparing the data access requirement to respective local memories of the one or more slave processors selecting a slave processor from the one or more slave processors based upon the comparing, and running the task on the selected slave processor.
Abstract translation: 公开了用于在具有至少一个主处理器和一个或多个从属处理器的非对称处理系统上更有效和灵活地调度任务的方法，系统和计算机可读存储介质。 一个示例实施例包括：确定任务的数据访问需求，将数据访问要求与一个或多个从属处理器的相应本地存储器进行比较，所述一个或多个从属处理器基于比较而从一个或多个从属处理器中选择从属处理器，并且执行任务 在所选的从属处理器上。
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