公开(公告)号：US09251081B2

公开(公告)日：2016-02-02

申请号：US13957105

申请日：2013-08-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai K. Chang ,  Yasuko Eckert ,  Gabriel H. Loh ,  Lisa R. Hsu

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0848 ,  G06F12/122 ,  Y02D10/13

Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.

公开(公告)号：US20150039833A1

公开(公告)日：2015-02-05

申请号：US13957105

申请日：2013-08-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai K. Chang ,  Yasuko Eckert ,  Gabriel H. Loh ,  Lisa R. Hsu

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0848 ,  G06F12/122 ,  Y02D10/13

Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.

Abstract translation: 一种用于在高速缓冲存储器中有效地降低存储器的电力以降低功耗的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，每个存储体包括多个缓存集。 响应于对高速缓存阵列中的多个存储体的第一存储体断电的请求，高速缓存控制器在第一存储体中选择给定类型的高速缓存行，并且确定所选高速缓存行的各个参考位置是否超过 阈。 如果超过阈值，则将所选择的高速缓存行迁移到高速缓存阵列中的第二组。 如果不超过阈值，则将所选的高速缓存行写回低级存储器。