公开(公告)号：US10008439B2

公开(公告)日：2018-06-26

申请号：US15205991

申请日：2016-07-08

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Sam Ziqun Zhao ,  Sam Komarapalayam Karikalan ,  Edward Law ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/81

摘要： Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

公开(公告)号：US20180233440A1

公开(公告)日：2018-08-16

申请号：US15911500

申请日：2018-03-05

申请人： AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

发明人： Edward Law ,  Sam Ziqun Zhao ,  Kunzhong Hu ,  Rezaur Rahman Khan

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/06135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00014

摘要： A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

公开(公告)号：US20190123007A1

公开(公告)日：2019-04-25

申请号：US15792922

申请日：2017-10-25

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Sam Ziqun Zhao ,  Liming Tsau ,  Edward Law ,  Andy Brotman

IPC分类号： H01L23/00 ,  H01L23/50 ,  H01L23/31

摘要： An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug.