SECURE CHIPS WITH SERIAL NUMBERS
    2.
    发明申请

    公开(公告)号:US20200350259A1

    公开(公告)日:2020-11-05

    申请号:US16927805

    申请日:2020-07-13

    Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non--common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.

    Apparatus for transferring a substrate in a lithography system

    公开(公告)号:USRE48903E1

    公开(公告)日:2022-01-25

    申请号:US16281179

    申请日:2019-02-21

    Abstract: An apparatus for transferring a target, such as a substrate or a substrate support structure onto which a substrate has been clamped, from a substrate transfer system to a vacuum chamber of a lithography system. The apparatus comprises a load lock chamber for transferring the target into and out of the vacuum chamber. The load lock chamber comprises a first wall with a first passage providing access between a robot space and the interior of the load lock chamber, a second wall with a second passage providing access between the interior of the load lock chamber and the vacuum chamber, and plurality of handling robots for transferring the targets comprising: a first handling robot movable within the robot space to access the substrate transfer system and the first passage; and a second handling robot movable within the load lock chamber to access the first passage and the second passage.

    Secure chips with serial numbers
    5.
    发明授权

    公开(公告)号:US10522472B2

    公开(公告)日:2019-12-31

    申请号:US15444369

    申请日:2017-02-28

    Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.

    Beam grid layout
    6.
    再颁专利

    公开(公告)号:USRE49952E1

    公开(公告)日:2024-04-30

    申请号:US16838976

    申请日:2020-04-02

    Abstract: A sub-beam aperture array for forming a plurality of sub-beams from one or more charged particle beams. The sub-beam aperture array comprises one or more beam areas, each beam area comprising a plurality of sub-beam apertures arranged in a non-regular hexagonal pattern, the sub-beam apertures arranged so that, when projected in a first direction onto a line parallel to a second direction, the sub-beam apertures are uniformly spaced along the line, and wherein the first direction is different from the second direction. The system further comprises a beamlet aperture array with a plurality of beamlet apertures arranged in one or more groups. The beamlet aperture array is arranged to receive the sub-beams and form a plurality of beamlets at the locations of the beamlet apertures of the beamlet array.

    Secure chips with serial numbers
    9.
    发明授权

    公开(公告)号:US10714427B2

    公开(公告)日:2020-07-14

    申请号:US15444396

    申请日:2017-02-28

    Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.

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