公开(公告)号：US20230207309A1

公开(公告)日：2023-06-29

申请号：US18117729

申请日：2023-03-06

申请人： ASM IP Holding B.V.

发明人： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Steven R.A. Van Aerde ,  Suvi Haukka ,  Atsuki Fukazawa ,  Hideaki Fukuda

IPC分类号： H01L21/02 ,  H01J37/32 ,  H01L21/762 ,  C23C16/455 ,  C23C16/04 ,  C23C16/40

CPC分类号： H01L21/0228 ,  H01J37/32009 ,  H01L21/76224 ,  H01L21/02274 ,  H01L21/02178 ,  H01L21/02299 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02219 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/045 ,  C23C16/402 ,  H01J2237/334 ,  H01J2237/3321

摘要： According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

公开(公告)号：US20160141176A1

公开(公告)日：2016-05-19

申请号：US14941322

申请日：2015-11-13

申请人： ASM IP Holding B.V.

发明人： Steven R.A. Van Aerde ,  Cornelius A. van der Jeugd ,  Theodorus G.M. Oosterlaken ,  Frank Huussen

IPC分类号： H01L21/02

CPC分类号： H01L21/02669 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76883

摘要： In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

公开(公告)号：US20160020094A1

公开(公告)日：2016-01-21

申请号：US14555379

申请日：2014-11-26

申请人： ASM IP Holding B.V.

发明人： Steven R.A. Van Aerde ,  Cornelius A. van der Jeugd ,  Theodorus G.M. Oosterlaken

IPC分类号： H01L21/02

CPC分类号： H01L21/02667 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/32055 ,  H01L21/76877

摘要： In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

摘要翻译： 在一些实施例中，形成硅填充开口，其在硅填充物中没有或少量出现空隙，同时保持光滑的暴露的硅表面。 在一些实施例中，衬底中的开口可以填充有硅，例如非晶硅。 沉积的硅可能具有内部空隙。 然后将沉积的硅暴露于硅迁移率抑制剂，例如含氧物质和/或半导体掺杂剂。 沉积的硅填充物随后退火。 在退火之后，空隙的尺寸可以减小，并且在一些实施例中，尺寸的这种减小可以发生到消除空隙的程度。

公开(公告)号：US20160020093A1

公开(公告)日：2016-01-21

申请号：US14335446

申请日：2014-07-18

申请人： ASM IP Holding B.V

发明人： Steven R.A. Van Aerde ,  Cornelius A. van der Jeugd ,  Theodorus G.M. Oosterlaken

IPC分类号： H01L21/02

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02669

摘要： In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

公开(公告)号：US20180286679A1

公开(公告)日：2018-10-04

申请号：US15476752

申请日：2017-03-31

申请人： ASM IP Holding B.V.

发明人： Kelly Houben ,  Steven R.A. Van Aerde ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC分类号： H01L21/033

CPC分类号： H01L21/0337

摘要： The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

公开(公告)号：US20180286672A1

公开(公告)日：2018-10-04

申请号：US15476702

申请日：2017-03-31

申请人： ASM IP Holding B.V.

发明人： Steven R.A. Van Aerde ,  Kelly Houben ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux

IPC分类号： H01L21/02 ,  H01L21/324 ,  H01L21/306

摘要： Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.

公开(公告)号：US20160093487A1

公开(公告)日：2016-03-31

申请号：US14497577

申请日：2014-09-26

申请人： ASM IP Holding B.V.

发明人： Frank HUUSSEN ,  Gijs DINGEMANS ,  Steven R.A. Van Aerde

IPC分类号： H01L21/02 ,  H01L21/673 ,  H01L21/285

CPC分类号： H01L21/0262 ,  C23C16/45523 ,  C23C16/4583 ,  C23C16/46 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32055 ,  H01L21/67303

摘要： An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or less is deposited on wafers accommodated in a wafer boat in a vertical furnace at a deposition temperature of the furnace while a deposition gas is flowing. During the first step, the temperature may be held substantially constant. In a second step, a temperature deviation or variation of at least 50° C. from the deposition temperature of the first step is applied and the furnace temperature is returned to the deposition temperature of the first step while the flow of the deposition gas is stopped. The first and second steps are repeated until a desired final film thickness is deposited.

摘要翻译： 本发明的示例性实施例提供了一种在半导体晶片上沉积膜的方法。 在第一步骤中，当沉积气体流动时，在炉的沉积温度下，将垂直炉中容纳在晶片舟皿中的晶片上沉积3μm或更小的膜厚度。 在第一步骤期间，温度可以保持基本恒定。 在第二步骤中，施加与第一步骤的沉积温度相比至少50℃的温度偏差或变化，并且炉温度返回到第一步骤的沉积温度，同时沉积气体的流动停止 。 重复第一和第二步骤，直到沉积所需的最终膜厚度。