公开(公告)号：US09343304B2

公开(公告)日：2016-05-17

申请号：US14497577

申请日：2014-09-26

申请人： ASM IP Holding B.V.

发明人： Frank Huussen ,  Gijs Dingemans ,  Steven R. A. Van Aerde

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/673

CPC分类号： H01L21/0262 ,  C23C16/45523 ,  C23C16/4583 ,  C23C16/46 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32055 ,  H01L21/67303

摘要： An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or less is deposited on wafers accommodated in a wafer boat in a vertical furnace at a deposition temperature of the furnace while a deposition gas is flowing. During the first step, the temperature may be held substantially constant. In a second step, a temperature deviation or variation of at least 50° C. from the deposition temperature of the first step is applied and the furnace temperature is returned to the deposition temperature of the first step while the flow of the deposition gas is stopped. The first and second steps are repeated until a desired final film thickness is deposited.

摘要翻译： 本发明的示例性实施例提供了一种在半导体晶片上沉积膜的方法。 在第一步骤中，当沉积气体流动时，在炉的沉积温度下，将垂直炉中容纳在晶片舟皿中的晶片上沉积3μm或更小的膜厚度。 在第一步骤期间，温度可以保持基本恒定。 在第二步骤中，施加与第一步骤的沉积温度相比至少50℃的温度偏差或变化，并且炉温度返回到第一步骤的沉积温度，同时沉积气体的流动停止 。 重复第一和第二步骤，直到沉积所需的最终膜厚度。

公开(公告)号：US20160141176A1

公开(公告)日：2016-05-19

申请号：US14941322

申请日：2015-11-13

申请人： ASM IP Holding B.V.

发明人： Steven R.A. Van Aerde ,  Cornelius A. van der Jeugd ,  Theodorus G.M. Oosterlaken ,  Frank Huussen

IPC分类号： H01L21/02

CPC分类号： H01L21/02669 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76883

摘要： In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

公开(公告)号：US09837271B2

公开(公告)日：2017-12-05

申请号：US14941322

申请日：2015-11-13

申请人： ASM IP Holding B.V.

发明人： Steven R. A. Van Aerde ,  Cornelius A. van der Jeugd ,  Theodorus G. M. Oosterlaken ,  Frank Huussen

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  C23C16/24 ,  C23C16/04 ,  C23C16/56 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L21/02669 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76883

摘要： In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.