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    Redundancy schemes for memory cell repair
    2.
    发明授权
    Redundancy schemes for memory cell repair 有权

    公开(公告)号：US09911510B1

    公开(公告)日：2018-03-06

    申请号：US15288832

    申请日：2016-10-07

    Applicant: ARM Limited

    Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

    IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

    CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

    Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

    Corner Database Generator
    4.
    发明申请
    Corner Database Generator 审中-公开

    公开(公告)号：US20180173822A1

    公开(公告)日：2018-06-21

    申请号：US15387373

    申请日：2016-12-21

    Applicant: ARM Limited

    Inventor： Hongwei Zhu ,  Mouli Rajaram Chollangi ,  Hemant Joshi ,  Yew Keong Chong ,  Satinderjit Singh ,  Betsie Jacob ,  Neeraj Dogra ,  Sriram Thyagarajan

    IPC: G06F17/50 ,  G06F17/30

    CPC classification number: G06F17/5009 ,  G06F17/30289 ,  G06F17/5068 ,  G06F2217/12

    Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.

    Bitline write assist circuitry
    6.
    发明授权
    Bitline write assist circuitry 有权

    公开(公告)号：US10217496B1

    公开(公告)日：2019-02-26

    申请号：US15907951

    申请日：2018-02-28

    Applicant: Arm Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Bo Zheng ,  Fakhruddin Ali Bohra

    IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/419

    Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

    Corner database generator
    7.
    发明授权
    Corner database generator 有权

    公开(公告)号：US10140399B2

    公开(公告)日：2018-11-27

    申请号：US15387373

    申请日：2016-12-21

    Applicant: ARM Limited

    Inventor： Hongwei Zhu ,  Mouli Rajaram Chollangi ,  Hemant Joshi ,  Yew Keong Chong ,  Satinderjit Singh ,  Betsie Jacob ,  Neeraj Dogra ,  Sriram Thyagarajan

    IPC: G06F17/50 ,  G06F17/30

    Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.

    Integrated circuit using shaping and timing circuitries
    9.
    发明授权
    Integrated circuit using shaping and timing circuitries 有权

    公开(公告)号：US10074410B2

    公开(公告)日：2018-09-11

    申请号：US15282532

    申请日：2016-09-30

    Applicant: ARM Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

    IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

    Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

    Integrated Circuit Using Shaping and Timing Circuitries
    10.
    发明申请
    Integrated Circuit Using Shaping and Timing Circuitries 审中-公开

    公开(公告)号：US20180096715A1

    公开(公告)日：2018-04-05

    申请号：US15282532

    申请日：2016-09-30

    Applicant: ARM Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

    IPC: G11C7/12 ,  G11C5/14 ,  G11C7/22

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

    Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

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