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    Apparatus and method for issuing access requests to a memory controller
    5.
    发明授权
    Apparatus and method for issuing access requests to a memory controller 有权

    公开(公告)号：US10956045B2

    公开(公告)日：2021-03-23

    申请号：US14969414

    申请日：2015-12-15

    Applicant: ARM Limited

    Inventor： Andreas Hansson ,  Ian Rudolf Bratt

    IPC: G06F3/06 ,  G06F13/16 ,  G06F12/12

    Abstract: An apparatus and method are provided for issuing access requests to a memory controller for a memory device whose memory structure consists of a plurality of sub-structures. The apparatus has a request interface for issuing access requests to the memory controller, each access request identifying a memory address. Within the apparatus static abstraction data is stored providing an indication of one or more of the sub-structures of the memory device, and the apparatus also stores an indication of outstanding access requests issued from the request interface. Next access request selection circuitry is then arranged to select from a plurality of candidate access requests a next access request to issue from the request interface. That selection is dependent on sub-structure indication data that is derived from application of an abstraction data function, using the static abstraction data, to the memory addresses of the candidate access requests and the outstanding access requests. Such an approach enables the apparatus to provide a series of access requests to the memory controller with the aim of enabling the memory controller to perform a more optimal access sequence with regard to the memory device.

    Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands
    6.
    发明授权
    Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands 有权

    公开(公告)号：US10339050B2

    公开(公告)日：2019-07-02

    申请号：US15273743

    申请日：2016-09-23

    Applicant: ARM Limited

    Inventor： Andreas Hansson ,  Wendy Arnott Elsasser ,  Michael Andrew Campbell

    IPC: G06F12/06 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0888 ,  G06F13/42

    Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.

    Memory controller and method for controlling a memory device to process access requests issued by at least one master device
    8.
    发明授权
    Memory controller and method for controlling a memory device to process access requests issued by at least one master device 有权

    公开(公告)号：US11243898B2

    公开(公告)日：2022-02-08

    申请号：US14449689

    申请日：2014-08-01

    Applicant: ARM Limited

    Inventor： Andreas Hansson ,  Aniruddha Nagendran Udipi ,  Neha Agarwal

    IPC: G06F13/18 ,  G06F13/16 ,  G11C8/12

    Abstract: A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions. Such an approach enables significant performance and energy savings to be realized in control of the memory device, without requiring the contents of the pending access requests storage to be directly monitored by the access control circuitry.

    Storage circuitry responsive to a tag-matching command
    9.
    发明授权
    Storage circuitry responsive to a tag-matching command 有权

    公开(公告)号：US10860495B2

    公开(公告)日：2020-12-08

    申请号：US16464019

    申请日：2017-09-15

    Applicant: ARM LIMITED

    Inventor： Andreas Hansson ,  Nikos Nikoleris ,  Wendy Arnott Elsasser

    IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0895 ,  G06F12/0864 ,  G11C11/16 ,  G11C11/406

    Abstract: Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

    Memory unit and method of operation of a memory unit to handle operation requests
    10.
    发明授权
    Memory unit and method of operation of a memory unit to handle operation requests 有权

    公开(公告)号：US11010297B2

    公开(公告)日：2021-05-18

    申请号：US16321057

    申请日：2017-06-26

    Applicant: ARM LIMITED

    Inventor： Andreas Hansson

    IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0893 ,  G06F15/78 ,  G06F9/38

    Abstract: A memory unit includes a data storage to store data, an operation controller to receive operation requests issued by an upstream source, a downstream capabilities storage to store an indication of operations performable by at least one downstream memory unit, and processing circuitry to perform operations on data stored in the data storage under control of the operation controller. When an operation request to perform an operation on target data is received from the upstream request source, the operation controller is arranged to determine when to control the processing circuitry to perform the operation, and when to forward the operation to a downstream memory unit in dependence on whether the target data is stored in the data storage unit and the indication of operations performable by at least one downstream memory unit. This allows for operations to be executed at a suitable location within a memory system, taking into account not only where the data resides, but also the complexity of the operation and the capabilities of the processing circuitry provided at various memory locations within the memory system.

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