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公开(公告)号：US10558580B2
公开(公告)日：2020-02-11
申请号：US15273398
申请日：2016-09-22
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Haining Zhang , Karan Sanghi , Saurabh Garg
Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
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2.发明申请公开(公告)号：US20190034368A1
公开(公告)日：2019-01-31
申请号：US16056374
申请日：2018-08-06
Applicant: Apple Inc.
Inventor： Karan Sanghi , Vladislav Petkov , Radha Kumar Pulyala , Saurabh Garg , Haining Zhang
CPC classification number: G06F13/28 , G06F13/4027 , Y02D10/14 , Y02D10/151
Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
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3.发明申请公开(公告)号：US20180129269A1
公开(公告)日：2018-05-10
申请号：US15647063
申请日：2017-07-11
Applicant: Apple Inc.
Inventor： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Richard Solotke
Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
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公开(公告)号：US20170249164A1
公开(公告)日：2017-08-31
申请号：US15273413
申请日：2016-09-22
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Haining Zhang , Karan Sanghi , Saurabh Garg
IPC: G06F9/44 , G06F12/1009 , G06F12/14 , G06F13/42
Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
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5.发明申请METHODS AND APPARATUS FOR CONTROLLED RECOVERY OF ERROR INFORMATION BETWEEN INDEPENDENTLY OPERABLE PROCESSORS 有权控制恢复独立运行处理器之间的错误信息的方法和装置公开(公告)号：US20160224442A1
公开(公告)日：2016-08-04
申请号：US14870923
申请日：2015-09-30
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Vladislav Petkov , Haining Zhang
CPC classification number: G06F11/2028 , G06F13/4022 , G06F13/4221 , G06F2201/805
Abstract: Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.
Abstract translation: 用于在两个（或多个）可独立操作的处理器之间控制恢复错误信息的方法和装置。 本公开提供了在致命错误的情况下保留错误信息，在独立可操作的处理器之间协调复位条件并且实现用于在一系列潜在致命错误中进行错误信息恢复的一致框架的解决方案。 在一个示例性实施例中，应用处理器（AP）和基带处理器（BB）实现中止处理器和掉电处理程序序列，其能够在广泛的崩溃情况下进行错误恢复。 在一种变型中，AP和BB之间的信号断言使AP能够在错误恢复过程成功完成后重置BB。
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Patent Agency Ranking
公开(公告)号：US11809258B2
公开(公告)日：2023-11-07
申请号：US16820307
申请日：2020-03-16
Applicant: Apple Inc.
Inventor： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Richard Solotke
IPC: G06F1/26 , G06F1/32 , G06F1/3234 , G06F13/40 , G06F13/42 , G06F1/3203 , G06F1/3287 , G06F9/30 , G06F9/4401 , G06F1/24
CPC classification number: G06F1/325 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F9/3004 , G06F9/4411 , G06F9/4418 , G06F13/404 , G06F13/4221 , G06F13/4273 , G06F13/4278 , G06F1/24 , Y02D10/00
Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
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公开(公告)号：US10572390B2
公开(公告)日：2020-02-25
申请号：US15273413
申请日：2016-09-22
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Haining Zhang , Karan Sanghi , Saurabh Garg
Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
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公开(公告)号：US10551902B2
公开(公告)日：2020-02-04
申请号：US15647088
申请日：2017-07-11
Applicant: Apple Inc.
Inventor： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Richard Solotke
IPC: G06F1/00 , G06F1/3234 , G06F1/3287 , G06F9/30 , G06F9/4401 , G06F13/42
Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
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公开(公告)号：US20190227944A1
公开(公告)日：2019-07-25
申请号：US16259957
申请日：2019-01-28
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Haining Zhang , Karan Sanghi , Saurabh Garg
Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.
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公开(公告)号：US10198364B2
公开(公告)日：2019-02-05
申请号：US15271102
申请日：2016-09-20
Applicant: Apple Inc.
Inventor： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Haining Zhang
IPC: G06F12/00 , G06F12/14 , G06F12/1081
Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.
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