公开(公告)号：US09931813B2

公开(公告)日：2018-04-03

申请号：US12774731

申请日：2010-05-06

Applicant: Kuan-Neng Chen ,  Wei-Chung Lo ,  Cheng-Ta Ko

Inventor： Kuan-Neng Chen ,  Wei-Chung Lo ,  Cheng-Ta Ko

IPC: B32B15/01 ,  B32B9/04 ,  B32B7/04 ,  B32B7/12 ,  B32B9/00 ,  B32B27/28 ,  B32B3/08

CPC classification number: B32B9/04 ,  B32B3/08 ,  B32B7/04 ,  B32B7/12 ,  B32B9/00 ,  B32B15/01 ,  B32B27/283 ,  B32B2307/714 ,  Y10T156/10 ,  Y10T428/12771 ,  Y10T428/31678

Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.

公开(公告)号：US08810031B2

公开(公告)日：2014-08-19

申请号：US12982046

申请日：2010-12-30

Applicant: Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

Inventor： Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/552 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.

Abstract translation: 提供具有堆叠结构的电子设备。 电子设备包括第一电子层，设置在第一电子层上的第二电子层和至少一个柱。 第一电子层具有第一界面，并且包括第一基板和设置在第一基板上的第一装置层。 第一接口位于第一基板和第一器件层之间，并且第一器件层具有与第一接口相对的表面。 该柱布置在第​​一器件层中，并且从第一界面延伸到第一器件层的表面。

公开(公告)号：US07948072B2

公开(公告)日：2011-05-24

申请号：US12180360

申请日：2008-07-25

Applicant: Ra-Min Tain ,  Shu-Ming Chang ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee ,  Chi-Shih Chang

Inventor： Ra-Min Tain ,  Shu-Ming Chang ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee ,  Chi-Shih Chang

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/562 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.

Abstract translation: 提供了其中形成有密封结构的晶片到晶片堆叠。 晶片堆叠包括第一晶片，其包括第一衬底和其上具有至少一个芯片和至少一个低k​​材料层的第一器件层，设置在第一晶片上方并具有第二衬底的第二晶片，以及闭合 结构设置在所述至少一个芯片上并且布置在所述至少一个芯片的切割边缘内，其中所述封闭结构从所述第一器件层的远离所述第一衬底的一侧延伸到与所述第一衬底相邻的另一侧 。

公开(公告)号：US20070090490A1

公开(公告)日：2007-04-26

申请号：US11471165

申请日：2006-06-20

Applicant: Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

Inventor： Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

IPC: H01L23/12 ,  H01L21/58

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L23/642 ,  H01L24/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.

Abstract translation: 提供了一种新颖的三维晶片叠层及其制造方法。 三维晶片堆叠包括具有第一基板的第一晶片和在其上具有至少一个芯片的第一器件层，设置在第一晶片上方并具有第二基板的第二晶片，以及布置在第一基板之间并从其延伸的至少一个基座 第一衬底到第二衬底。 布置在器件层中的基座用于防止存在于器件层中的低k材料被应力损坏。

公开(公告)号：US08915634B2

公开(公告)日：2014-12-23

申请号：US13590202

申请日：2012-08-21

Applicant: Chao-Kai Hsu ,  Yu-Hua Chen ,  Wei-Chung Lo

Inventor： Chao-Kai Hsu ,  Yu-Hua Chen ,  Wei-Chung Lo

IPC: F21V7/04 ,  F21V13/04 ,  F21S2/00 ,  F21V5/00 ,  F21Y105/00 ,  F21Y101/02

CPC classification number: F21V5/002 ,  F21S2/00 ,  F21V13/04 ,  F21Y2105/00 ,  F21Y2115/10 ,  G02B6/0021 ,  G02B6/0036 ,  G02B6/0061 ,  G02B6/0068 ,  G02B6/0073 ,  G02B6/0078 ,  G02B6/0083 ,  G02B6/009

Abstract: A plane light source including a circuit substrate, a plurality of sets of side-view light-emitting devices (LEDs), and a diffusive light-guiding layer is provided. The side-view LEDs are arranged in array over the circuit substrate and are electrically connected with the circuit substrate. The diffusive light-guiding layer covers the side-view LEDs, wherein the diffusive light-guiding layer includes a plurality of diffusive light-guiding units arranged in array and connected to each other. Each of the diffusive light-guiding units is respectively corresponded to illumination coverage of one set of side-view LEDs. Each set of side-view LEDs at least includes two side-view LEDs for emitting light respectively along two different directions and towards into one single diffusive light-guiding units.

Abstract translation: 提供了包括电路基板，多组侧视发光装置（LED）和漫射光导层的平面光源。 侧视LED被布置在电路基板上并且与电路基板电连接。 漫射光导层覆盖侧视LED，其中漫射光导层包括排列成阵列并彼此连接的多个漫射导光单元。 每个漫射光导单元分别对应于一组侧视LED的照明覆盖。 每组侧视LED至少包括两个侧视LED，用于分别沿着两个不同方向发射光并朝向一个单个漫射光导单元。

公开(公告)号：US20070108629A1

公开(公告)日：2007-05-17

申请号：US11652088

申请日：2007-01-11

Applicant: Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

Inventor： Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract translation: 提供晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和相邻层之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和相邻层之间的界面将崩溃以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US20120313133A1

公开(公告)日：2012-12-13

申请号：US13224607

申请日：2011-09-02

Applicant: KUAN-NENG CHEN ,  CHENG-TA KO ,  WEI-CHUNG LO

Inventor： KUAN-NENG CHEN ,  CHENG-TA KO ,  WEI-CHUNG LO

IPC: H01L33/62 ,  H01L33/48

CPC classification number: H01L33/62 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/167 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00013 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.

Abstract translation: 异质结构包含IC和LED。 最初提供IC和LED。 IC具有至少一个第一导电块和至少一个第一连接块。 IC与第一导电块电连接。 LED的第一面具有至少一个第二导电块和至少一个第二连接块。 LED电连接到第二导电块。 随后，第一导电块和第一连接块分别连接到第二导电块和第二连接块。 第一导电块与第二导电块电连接并形成异质结构。 该系统同时提供IC和LED的散热和电通信功能，从而产生高密度多功能异质结构。

公开(公告)号：US20120178212A1

公开(公告)日：2012-07-12

申请号：US13424926

申请日：2012-03-20

Applicant: Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

Inventor： Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

IPC: H01L21/98

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L23/642 ,  H01L24/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.

Abstract translation: 提供了一种新颖的三维晶片叠层及其制造方法。 三维晶片堆叠包括具有第一基板的第一晶片和在其上具有至少一个芯片的第一器件层，设置在第一晶片上方并具有第二基板的第二晶片，以及布置在第一基板之间并从其延伸的至少一个基座 第一衬底到第二衬底。 布置在器件层中的基座用于防止存在于器件层中的低k材料被应力损坏。

公开(公告)号：US08049330B2

公开(公告)日：2011-11-01

申请号：US11284936

申请日：2005-11-23

Applicant: Ra-Min Tain ,  Wei-Chung Lo ,  Li-Cheng Shen

Inventor： Ra-Min Tain ,  Wei-Chung Lo ,  Li-Cheng Shen

IPC: H01L23/36 ,  H01L23/373

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A structure of light emitting diode (LED) wafer-level chip scale packaging (WL-CSP) is disclosed. The process of making the same is also provided in this invention. The LED CSP utilizes the through hole metal filling to enhance heat conduction between the LED die and its carrier substrate. The CSP structure is achieved by bonding pre-processed through-hole-filling carrier substrate against the flip-chip LED wafer.

Abstract translation: 公开了一种发光二极管（LED）晶片级芯片级封装（WL-CSP）的结构。 本发明也提供了制备该方法的方法。 LED CSP利用通孔金属填充来增强LED管芯与其载体衬底之间的热传导。 通过将预处理的通孔填充载体衬底与倒装芯片LED晶片结合来实现CSP结构。

公开(公告)号：US08039935B2

公开(公告)日：2011-10-18

申请号：US11652088

申请日：2007-01-11

Applicant: Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

Inventor： Shu-Ming Chang ,  Lee-Cheng Shen ,  Wei-Chung Lo

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract translation: 提供晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和相邻层之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和相邻层之间的界面将崩溃以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。