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公开(公告)号：US12123698B1
公开(公告)日：2024-10-22
申请号：US18739436
申请日：2024-06-11
申请人： UNITY SEMICONDUCTOR
CPC分类号： G01B11/02 , G01B11/26 , G01B2210/56
摘要： A method for characterizing a structure etched in a first substrate surface, the structure extending along a longitudinal direction, z, into the substrate, the method implemented by a system including a light source emitting an illumination beam with a wavelength transmitted through the substrate, and an imaging device positioned to face a second substrate surface opposite the first surface, the method including illuminating at least one structure with the illumination beam, subsequently positioning an object plane of the imaging device at at least two different longitudinal positions; acquiring at least one image of the structure at each of the longitudinal positions, the images being acquired through the substrate; measuring data relating to a lateral dimension of the structure from each acquired image at each of the longitudinal positions; and determining longitudinal data relating to a longitudinal shape of the structure from the lateral data of at least two longitudinal positions.
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公开(公告)号：US11942379B1
公开(公告)日：2024-03-26
申请号：US18359661
申请日：2023-07-26
申请人： Unity Semiconductor
CPC分类号： H01L22/12 , G01N21/9501 , H01L22/20
摘要： A measurement system and an inspection method for detecting a defective bonding interface in a sample substrate including at least one element disposed on a support. The method comprises: placing the sample substrate in the measurement system, establishing an inclination map of the exposed surface, analyzing the inclination map and identifying a zone or zones of the exposed surface whose inclinations deviate by more than a given threshold from the inclination of the reference surface; and detecting the presence of a defective bond between the element and the support, depending on the result of the analysis of the inclination map.
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公开(公告)号：US11713960B2
公开(公告)日：2023-08-01
申请号：US17296117
申请日：2019-11-28
申请人： UNITY SEMICONDUCTOR
IPC分类号： G01B9/0209 , G01B9/02 , G01B11/06
CPC分类号： G01B9/0209 , G01B9/02083 , G01B9/02088 , G01B11/0625 , G01B2210/56
摘要： A method for measuring a surface of an object including at least one structure using low coherence optical interferometry, the method including the steps of acquiring an interferometric signal at a plurality of measurement points in a field of view and, for at least one measurement point, attributing the interferometric signal acquired to a class of interferometric signals from a plurality of classes, each of the classes being associated with a reference interferometric signal representative of a typical structure; and analysing the interferometric signal to derive therefrom an item of information on the structure at the measurement point, as a function of its class.
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公开(公告)号：US11069386B2
公开(公告)日：2021-07-20
申请号：US16869816
申请日：2020-05-08
IPC分类号： G11C7/00 , G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , G11C8/10 , G11C8/12 , G11C7/04 , B82Y30/00
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
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公开(公告)号：US10790334B2
公开(公告)日：2020-09-29
申请号：US15633050
申请日：2017-06-26
发明人： Bruce Lynn Bateman
摘要： An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
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公开(公告)号：US10788993B2
公开(公告)日：2020-09-29
申请号：US16811401
申请日：2020-03-06
发明人： Chang Hua Siau
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
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公开(公告)号：US10650870B2
公开(公告)日：2020-05-12
申请号：US16276333
申请日：2019-02-14
IPC分类号： G11C7/00 , G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , G11C8/10 , G11C8/12 , G11C7/04 , B82Y30/00
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
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8.发明申请公开(公告)号：US20190252011A1
公开(公告)日：2019-08-15
申请号：US16276333
申请日：2019-02-14
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
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公开(公告)号：US20190219520A1
公开(公告)日：2019-07-18
申请号：US16319455
申请日：2017-06-01
申请人： UNITY SEMICONDUCTOR
发明人： Sylvain PETITGRAND
IPC分类号： G01N21/95 , G01B11/06 , H01L21/673
CPC分类号： G01N21/9501 , G01B11/0608 , G01R31/2891 , H01L21/67346
摘要： A device for positioning an integrated circuit wafer includes: a base, called upper, and a base, called lower, arranged at a distance from one another in a direction, called vertical, so as to leave a free space between the bases; a support, provided to be mobile between the upper and lower bases, and including a location for receiving the wafer to be inspected; at least one first means apparatus for positioning the support in the vertical direction against, or by cooperation with, the upper base; and at least one second means apparatus for positioning the support in the vertical direction against, or by cooperation with, the lower base. Also provided is an inspection equipment for an integrated circuit wafer implementing such a positioning device.
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公开(公告)号：US10260868B2
公开(公告)日：2019-04-16
申请号：US15515407
申请日：2015-09-29
申请人： UNITY SEMICONDUCTOR
摘要： An electronic wafer inspecting method includes: rotating the wavelength transparent wafer, emitting, from a light source coupled with an interferometric device, two light beams, to form, a measurement volume and having a variable inter-fringe distance within the volume, a time signature of a defect intersecting the measurement volume depending on an inter-fringe distance where the defect intersects the volume, the device and the wafer arranged so that the measurement volume extends into a wafer region, collecting the light scattered by the wafer region, emitting a signal representing the variation in the intensity of the collected light per time, detecting in the signal, a frequency of the intensity, the frequency being the time of the passage of a defect through the measurement volume, determining, based on the value of the inter-fringe distance at the location where the defect passes, the position of the defect.
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