公开(公告)号：US07902835B2

公开(公告)日：2011-03-08

申请号：US11916232

申请日：2006-05-18

申请人： Takayuki Nakamura ,  Takashi Sekino

发明人： Takayuki Nakamura ,  Takashi Sekino

IPC分类号： G01R29/26 ,  G01R27/28

CPC分类号： H04L25/03343 ,  H04L25/0288

摘要： A transmission line driving circuit that can support a high-rate signal transmission and further can perform appropriate loss compensation in accordance with a signal pattern. A transmission line driving circuit 1 comprises a plurality of driver input circuits 20 that serve as signal analyzing unit for analyzing the content of the signal pattern of an input signal; a plurality of lowpass filters 30; a plurality of gain adjusting circuits 40; a plurality of adders 50; and adder 52; and a driver output circuit 60 that outputs, in accordance with a signal analysis result, a signal the phase of which has been adjusted in such a direction that cancels the timing deviation caused by a loss occurring when the input signal is transmitted to the transmission path. The output signal from the driver output circuit 60 is transmitted to the transmission path 2.

摘要翻译： 一种传输线路驱动电路，其能够支持高速率信号传输，并且还可以根据信号模式执行适当的损耗补偿。 传输线驱动电路1包括多个驱动器输入电路20，其用作用于分析输入信号的信号模式的内容的信号分析单元; 多个低通滤波器30， 多个增益调整电路40; 多个加法器50; 和加法器52; 以及驱动器输出电路60，其根据信号分析结果输出其相位已经被调整的信号，该信号在消除由输入信号被发送到传输路径时发生的损失引起的定时偏移的方向上 。 来自驱动器输出电路60的输出信号被发送到传输路径2。

公开(公告)号：US20100201421A1

公开(公告)日：2010-08-12

申请号：US11916247

申请日：2006-06-18

申请人： Takayuki Nakamura ,  Takashi Sekino

发明人： Takayuki Nakamura ,  Takashi Sekino

IPC分类号： H03K5/156

CPC分类号： H03K5/156 ,  G01R31/2841 ,  G01R31/31709 ,  H03K3/84 ,  H03K7/08

摘要： A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pattern of an input signal; a plurality of gain adjusting circuits 30; a plurality of lowpass filters 40; a plurality of adders 50; an adder 52; and a driver output circuit 60 that outputs a signal obtained by adjusting, in accordance with a signal analysis result, the phase of the input signal in such a direction in which the change timing deviates when the input signal is transmitted to the transmission line. Thus, the phase of an input signal is adjusted, thereby adding the jitter to the input signal.

摘要翻译： 抖动发生电路，其中可以使用简单的结构来产生模式效果抖动。 抖动发生电路1包括用作​​信号分析单元的驱动器输入电路20，用于分析输入信号的信号模式的内容; 多个增益调整电路30; 多个低通滤波器40; 多个加法器50; 加法器52; 以及驱动器输出电路60，其输出通过根据信号分析结果，当输入信号被发送到传输线时，在改变定时偏离的方向上调整输入信号的相位而获得的信号。 因此，输入信号的相位被调整，从而将抖动加到输入信号上。

公开(公告)号：US20090146677A1

公开(公告)日：2009-06-11

申请号：US12136049

申请日：2008-06-10

申请人： NAOKI MATSUMOTO ,  TAKASHI SEKINO

发明人： NAOKI MATSUMOTO ,  TAKASHI SEKINO

IPC分类号： G01R31/02

CPC分类号： G01R31/31924 ,  G01R31/3191

摘要： There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch.

摘要翻译： 提供了一种测试装置，包括将测试信号输出到被测设备的驱动器，切换是否将驱动器连接到被测器件的第一开关，比较器，经由该测试装置从被测器件接收输出信号 第一开关，将输出信号的电压与规定的基准电压进行比较，将基准电压输入到比较器的基准电压输入部，设置在基准电压输入部和比较器之间的第二开关， 电阻在其一端连接到比较器和第二开关之间的连接点，另一端连接到预定电位。 这里，驱动器的输出电阻和第一开关的导通电阻之间的电阻比基本上等于虚拟电阻和第二开关的导通电阻之间的电阻比。

公开(公告)号：US07512872B2

公开(公告)日：2009-03-31

申请号：US11600676

申请日：2006-11-16

申请人： Toshiaki Awaji ,  Takashi Sekino ,  Takayuki Nakamura

发明人： Toshiaki Awaji ,  Takashi Sekino ,  Takayuki Nakamura

IPC分类号： G11B27/00 ,  H03M13/00 ,  G01R31/28

CPC分类号： G01R31/31922 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/31727

摘要： The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase difference between the first and second delay clock signals to a desired phase difference; a deciding section that decides the quality of the data signal from the DUT based on a result obtained by acquiring the delay data signal when the second delay clock signal is changed.

摘要翻译： 该装置包括：第一可变延迟电路，用于延迟来自被测器件（DUT）的数据信号以输出延迟数据信号; 延迟时钟信号以输出第一延迟时钟信号的第二可变延迟电路; 基于参考时钟获取延迟数据信号的第一FF; 第二FF，其基于时钟获取第一延迟时钟信号; 第一延迟调整部分，调整第一和第二可变延迟电路中的至少一个的延迟量，使得当信号改变时第一和第二FF获取延迟数据信号和第一延迟时钟信号; 第三可变延迟电路，延迟所述时钟信号以输出第二延迟时钟信号; 第二延迟调整部分，当第二延迟时钟改变时，基于所获取的第一延迟时钟信号调整第三可变延迟电路的延迟量，该第一延迟时钟信号由第一延迟调整部分调整相位，以便调整相位 第一和第二延迟时钟信号之间的差异达到期望的相位差; 判定部，其基于当所述第二延迟时钟信号改变时通过获取所述延迟数据信号获得的结果来决定来自所述DUT的数据信号的质量。

公开(公告)号：US20090051347A1

公开(公告)日：2009-02-26

申请号：US11955230

申请日：2007-12-12

申请人： Katsumi Ochiai ,  Takashi Sekino

发明人： Katsumi Ochiai ,  Takashi Sekino

IPC分类号： G01R23/175

CPC分类号： G01R31/31922 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00045 ,  H03K2005/00071 ,  H03K2005/00156 ,  H03L7/18

摘要： A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal.

摘要翻译： 高频延迟电路，其可操作以输出延迟所需延迟时间的高频信号。 高频延迟电路包括：可变延迟电路，可操作用于接收频率低于高频信号的参考信号，并且预先输出从参考信号延迟所需延迟时间的延迟参考信号; 以及乘法器，用于产生高频信号，其中频率是延迟参考信号的频率乘以预定值，并且根据延迟参考信号的相位在定时输出所生成的高频信号。

公开(公告)号：US07459897B2

公开(公告)日：2008-12-02

申请号：US11706572

申请日：2007-02-14

申请人： Toshiaki Awaji ,  Takashi Sekino

发明人： Toshiaki Awaji ,  Takashi Sekino

IPC分类号： G01R19/00 ,  G01R27/08

CPC分类号： G01R31/31924 ,  G01R19/16557 ,  H04L25/0278 ,  H04L25/0292

摘要： The present invention provides a terminator circuit including a potential variation detecting section that detects a variation in a potential at an end point to which an input signal is supplied, and a first current generating section that reduces an overshoot at the end point which is caused by the application of the input signal, by pulling a current from the end point, when the potential variation detecting section detects a rise in the potential at the end point. Here, the potential variation detecting section includes a comparison potential generating section that generates a comparison potential based on a reference potential, and a potential comparing section that compares the comparison potential which has risen in accordance with the rise in the potential at the end point, with the reference potential, and outputs a result of the comparison.

摘要翻译： 本发明提供了一种终端电路，包括：电位变动检测部，其检测输入信号的终点处的电位变化;以及第一电流产生部，其减少由端部产生的端点处的过冲 当电位变化检测部分检测到终点处的电位升高时，通过从端点拉动电流来施加输入信号。 这里，电位变动检测部包括：比较电位生成部，其基于参考电位生成比较电位;以及电位比较部，其比较与终点上的电位上升相对应的比较电位， 具有参考电位，并输出比较结果。

公开(公告)号：US07394238B2

公开(公告)日：2008-07-01

申请号：US11101157

申请日：2005-04-07

申请人： Katsumi Ochiai ,  Takashi Sekino

发明人： Katsumi Ochiai ,  Takashi Sekino

IPC分类号： H03H11/26 ,  G01R27/28

CPC分类号： G01R31/31922 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00045 ,  H03K2005/00071 ,  H03K2005/00156 ,  H03L7/18

摘要： A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal.

摘要翻译： 高频延迟电路，其可操作以输出延迟所需延迟时间的高频信号。 高频延迟电路包括：可变延迟电路，可操作用于接收频率低于高频信号的参考信号，并且预先输出从参考信号延迟所需延迟时间的延迟参考信号; 以及乘法器，用于产生高频信号，其中频率是延迟参考信号的频率乘以预定值，并且根据延迟参考信号的相位在定时输出所生成的高频信号。

公开(公告)号：US20070262800A1

公开(公告)日：2007-11-15

申请号：US11759240

申请日：2007-06-07

申请人： Toshiaki Awaji ,  Takashi Sekino ,  Takayuki Nakamura

发明人： Toshiaki Awaji ,  Takashi Sekino ,  Takayuki Nakamura

IPC分类号： H03K3/84

CPC分类号： G01R31/31922 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/31727

摘要： There is provided an electronic device for receiving an input data signal and an input clock signal that indicates a timing to obtain the input data signal. The electronic device includes a first adjusting section that adjusts a phase difference between the input data signal and the input clock signal so as to be equal to a first phase difference, and outputs the resulting signals as a first data signal and a first clock signal, a phase varying section that outputs a second clock signal having a designated phase difference with respect to the first clock signal, and a second adjusting section that adjusts the phase difference of the second clock signal with respect to the first clock signal so as to be equal to a second phase difference, based on a result of obtaining the first clock signal at a varying timing of the second clock signal.

摘要翻译： 提供了一种用于接收输入数据信号的电子设备和指示获取输入数据信号的定时的输入时钟信号。 该电子设备包括第一调整部分，其将输入数据信号和输入时钟信号之间的相位差调整为等于第一相位差，并将所得信号作为第一数据信号和第一时钟信号输出， 输出相对于第一时钟信号具有指定的相位差的第二时钟信号的相变部分，以及相对于第一时钟信号调整第二时钟信号的相位差相等的第二调整部分 基于在第二时钟信号的变化定时获得第一时钟信号的结果，获得第二相位差。

公开(公告)号：US07123025B2

公开(公告)日：2006-10-17

申请号：US11202391

申请日：2005-08-11

申请人： Toshiaki Awaji ,  Takashi Sekino

发明人： Toshiaki Awaji ,  Takashi Sekino

IPC分类号： G01R27/28

CPC分类号： G01R19/10

摘要： There is provided a differential comparator circuit that is mounted on a test apparatus for testing a device under test outputting differential signals including noninverted signals and inverted signals. The differential comparator circuit includes: a difference signal subtracting circuit operable to compute and output a difference signal indicative of a difference between the noninverted signal and the inverted signal; a first threshold value subtracting circuit operable to compute and output a first threshold voltage indicative of a difference between a first comparative voltage generated based on ground potential of the device under test and a reference voltage generated based on the ground potential of the device under test; and a first comparing circuit operable to compare the difference signal and the first threshold voltage to output a comparison result.

摘要翻译： 提供了一种差分比较器电路，其安装在用于测试被测器件的测试装置上，输出包括非反相信号和反相信号的差分信号。 差分比较电路包括：差分信号减法电路，用于计算并输出表示非反相信号与反相信号之差的差分信号; 第一阈值减法电路，用于计算和输出表示基于被测器件的地电位产生的第一比较电压与基于被测器件的接地电位产生的参考电压之间的差的第一阈值电压; 以及第一比较电路，其可操作以比较差信号和第一阈值电压以输出比较结果。

公开(公告)号：US07013230B2

公开(公告)日：2006-03-14

申请号：US10757304

申请日：2004-01-14

申请人： Takashi Sekino

发明人： Takashi Sekino

IPC分类号： G06F19/00

CPC分类号： G01R31/31926

摘要： An input-output circuit sending and/or receiving a signal to and/or from an electronic device includes a driver for supplying a signal to the electronic device, a comparator provided parallel to the driver for receiving a signal from the electronic device, a relaying circuit provided between the comparator the electronic device in series with the comparator and the electronic device, a first transmission line for coupling the comparator and the relaying circuit electrically and a first switch for selecting either of short or open-circuited state of the first transmission line and the electronic device, wherein the impedance of the relaying circuit is larger than the impedance of the first transmission line.

摘要翻译： 向电子设备发送和/或从电子设备接收信号的输入输出电路包括用于向电子设备提供信号的驱动器，与驱动器并行设置的用于从电子设备接收信号的比较器， 在比较器之间提供与比较器和电子装置串联的电子装置的电路，用于电连接比较器和继电器的第一传输线和用于选择第一传输线的短路或开路状态的第一开关 以及所述电子设备，其中所述中继电路的阻抗大于所述第一传输线的阻抗。