公开(公告)号：US08697570B2

公开(公告)日：2014-04-15

申请号：US12941331

申请日：2010-11-08

Applicant: Taek-soo Jeon ,  Bong-hyun Kim ,  Won-seok Yoo ,  Jae-hong Seo ,  Ho-kyun An ,  Dae-hyun Kim

Inventor： Taek-soo Jeon ,  Bong-hyun Kim ,  Won-seok Yoo ,  Jae-hong Seo ,  Ho-kyun An ,  Dae-hyun Kim

IPC: H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/28525 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10823 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Abstract translation: 半导体器件包括具有导电区域的基板，形成在基板上的第一图案，具有导电区域露出的接触孔和接触孔中的接触插塞。 接触插塞包括第一和第二硅层。 在包括至少两个硅原子的第一化合物形成的第一硅层形成在接触孔中以接触导电区域的顶表面和第一图案的侧壁。 在第一硅层上形成由第二化合物构成的第二硅层，该第二化合物包含少于第一化合物的硅原子数的硅原子数，并填充接触孔的剩余空间，第二硅层 在接触孔的入口处与第一图案间隔开。

公开(公告)号：US20110124176A1

公开(公告)日：2011-05-26

申请号：US12954050

申请日：2010-11-24

Applicant: Han-Jin Lim ,  Jae-Hong Seo ,  Seok-Woo Nam ,  Bong-Hyun Kim ,  Taek-Soo Jeon

Inventor： Han-Jin Lim ,  Jae-Hong Seo ,  Seok-Woo Nam ,  Bong-Hyun Kim ,  Taek-Soo Jeon

IPC: H01L21/02

CPC classification number: H01L28/90 ,  H01L27/10817 ,  H01L27/10852

Abstract: In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Abstract translation: 在形成电容器的方法中，在具有插头的绝缘中间层上形成种子阻挡层和牺牲层。 通过牺牲层和种子塞子形成开口以露出塞子。 在开口的内壁上形成种子。 形成了覆盖开口内壁上的种子的下电极。 去除牺牲层和种子。 电介质层和上电极依次形成在下电极上。

公开(公告)号：US20070026596A1

公开(公告)日：2007-02-01

申请号：US11492400

申请日：2006-07-25

Applicant: Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

Inventor： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC: H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/823835 ,  H01L21/823842

Abstract: In a gate structure and a method of forming the same, a first conductive pattern is formed on a substrate and comprises a metal-containing material. A second conductive pattern is formed on the first conductive pattern, and the second conductive pattern comprises metal and silicon. A third conductive pattern is formed on the second conductive pattern, and the third conductive pattern comprises polysilicon. A gate conductive pattern of an n-type metal-oxide semiconductor (NMOS) transistor, a p-type MOS (PMOS) transistor and a complementary MOS (CMOS) transistor includes the gate structure. The second conductive pattern is interposed between the first and third conductive patterns and the third conductive pattern is prevented from making direct contact with the first conductive pattern, so that polysilicon in the third conductive pattern is sufficiently prevented from being chemically reacted with the metal in the first conductive pattern in advance, thereby improving electrical characteristics of the transistor.

Abstract translation: 在栅极结构及其形成方法中，第一导电图案形成在基板上并且包括含金属的材料。 在第一导电图案上形成第二导电图案，并且第二导电图案包括金属和硅。 在第二导电图案上形成第三导电图案，并且第三导电图案包括多晶硅。 n型金属氧化物半导体（NMOS）晶体管，p型MOS（PMOS）晶体管和互补MOS（CMOS）晶体管的栅极导电图案包括栅极结构。 第二导电图案插入在第一和第三导电图案之间，并且防止第三导电图案与第一导电图案直接接触，使得充分防止第三导电图案中的多晶硅与金属在化学反应中 第一导电图案，从而改善晶体管的电特性。

公开(公告)号：US20060273344A1

公开(公告)日：2006-12-07

申请号：US11400560

申请日：2006-04-07

Applicant: Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Pack ,  Taek-Soo Jeon

Inventor： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Pack ,  Taek-Soo Jeon

IPC: H01L29/74

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

公开(公告)号：US20060030097A1

公开(公告)日：2006-02-09

申请号：US11183651

申请日：2005-07-18

Applicant: Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

Inventor： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

Abstract translation: 在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。 可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。 可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。 还公开了相关门结构。

公开(公告)号：US20160315165A1

公开(公告)日：2016-10-27

申请号：US14955205

申请日：2015-12-01

Applicant: Dong-soo LEE ,  Hu-yong LEE ,  Won-keun CHUNG ,  Hoon-joo NA ,  Taek-soo JEON ,  Sang-jin HYUN

Inventor： Dong-soo LEE ,  Hu-yong LEE ,  Won-keun CHUNG ,  Hoon-joo NA ,  Taek-soo JEON ,  Sang-jin HYUN

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/512 ,  B82Y10/00 ,  H01L21/28185 ,  H01L21/823456 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

Abstract translation: 一种集成电路器件包括：衬底，其包括有源区，界面层包括有源区上的下绝缘层，所述下绝缘层掺杂有原子量等于或大于16的硫属元素;栅绝缘层， 界面层和栅极绝缘层上的栅电极。

公开(公告)号：US20090134448A1

公开(公告)日：2009-05-28

申请号：US12230835

申请日：2008-09-05

Applicant: Taek-Soo Jeon ,  Si-Young Choi ,  In-Sang Jeon ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Seung-Hoon Hong

Inventor： Taek-Soo Jeon ,  Si-Young Choi ,  In-Sang Jeon ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Seung-Hoon Hong

IPC: H01L29/68 ,  H01L21/336

CPC classification number: H01L29/4234 ,  H01L29/40117

Abstract: Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.

Abstract translation: 示例性实施例提供了一种非易失性半导体存储器件及其形成方法。 非易失性存储器件可以包括半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的第一阻挡绝缘层和第一阻挡绝缘层上的栅电极，其中 栅电极包括铝，并且第一阻挡绝缘层不包括铝。

公开(公告)号：US20070128775A1

公开(公告)日：2007-06-07

申请号：US11607600

申请日：2006-12-01

Applicant: Taek-Soo Jeon ,  Hag-ju Cho ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

Inventor： Taek-Soo Jeon ,  Hag-ju Cho ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC: H01L21/84

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a gate electrode of a MOS transistor including a tungsten carbon nitride layer is disclosed. After a high dielectric layer is formed on a substrate, a source gas including tungsten amine derivative flows onto the high dielectric layer. A tungsten carbon nitride layer is formed on the high dielectric layer by decomposing the source gas. Thereafter, a gate electrode is formed by patterning the tungsten carbon nitride layer. According to the present invention, a gate electrode having a work function of over 4.9 eV is formed.

Abstract translation: 公开了一种制造包括氮化钨层的MOS晶体管的栅电极的方法。 在基板上形成高电介质层之后，包含钨胺衍生物的源气体流到高电介质层上。 通过分解源气体，在高电介质层上形成碳氮化钨层。 此后，通过图案化氮化碳钨层来形成栅电极。 根据本发明，形成功函数为4.9eV以上的栅电极。

公开(公告)号：US20070111453A1

公开(公告)日：2007-05-17

申请号：US11497998

申请日：2006-08-01

Applicant: Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

Inventor： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC: H01L21/336 ,  H01L29/94

CPC classification number: H01L21/823842

Abstract: In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

Abstract translation: 在具有双栅极的半导体器件及其制造方法中，在具有第一和第二区域的半导体衬底上依次形成电介质层和第一和第二金属导电层。 形成在第二区域的第一金属导电层上的第二金属导电层被蚀刻以形成金属图案。 使用金属图案作为蚀刻掩模蚀刻第一金属导电层。 在电介质层和金属图案上形成多晶硅层。 第一栅极通过蚀刻第一区域的多晶硅层，金属图案和第一金属导电层的部分而形成。 通过蚀刻直接形成在第二区域的电介质层上的多晶硅层的一部分来形成第二栅电极。

公开(公告)号：US20070082415A1

公开(公告)日：2007-04-12

申请号：US11497972

申请日：2006-08-01

Applicant: Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

Inventor： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

IPC: H01L21/00

CPC classification number: H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

Abstract: A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.

Abstract translation: 具有双栅极的半导体器件形成在具有电介质层的衬底上。 在电介质层上形成第一金属导电层至第一厚度，并且退火以降低蚀刻速率。 在第一金属导电层上形成第二金属导电层至大于第一厚度的第二厚度。 使用蚀刻选择性去除在衬底的第二区域中形成的第二金属导电层的一部分。 具有包括第一和第二金属导电层的第一金属栅极的第一栅极结构形成在衬底的第一区域中。 具有第二金属栅极的第二栅极结构形成在第二区域中。 由于第一金属导电层，栅极电介质层不暴露于蚀刻化学品，因此其介电特性不劣化。