公开(公告)号：US09773784B2

公开(公告)日：2017-09-26

申请号：US13594296

申请日：2012-08-24

Applicant: Chieh-Chih Chen ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/761 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.

公开(公告)号：US08686509B2

公开(公告)日：2014-04-01

申请号：US13369643

申请日：2012-02-09

Applicant: Chien-Chih Chen ,  Li-Fan Chen ,  Cheng-Chi Lin ,  Shin-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chien-Chih Chen ,  Li-Fan Chen ,  Cheng-Chi Lin ,  Shin-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L23/62 ,  H01L21/82

CPC classification number: H01L27/027 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/861

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region and a second doped region. The first doped region comprises a first contact region. The first doped region and the first contact region have a first type conductivity. The second doped region comprises a second contact region. The second doped region and the second contact region have a second type conductivity opposite to the first type conductivity. The first doped region is adjacent to the second doped region.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括第一掺杂区和第二掺杂区。 第一掺杂区域包括第一接触区域。 第一掺杂区域和第一接触区域具有第一类型的导电性。 第二掺杂区域包括第二接触区域。 第二掺杂区域和第二接触区域具有与第一类型导电性相反的第二类型导电性。 第一掺杂区域与第二掺杂区域相邻。

公开(公告)号：US08648386B2

公开(公告)日：2014-02-11

申请号：US13222187

申请日：2011-08-31

Applicant: Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

Inventor： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC: H01L27/07

CPC classification number: H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract translation: 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US08610209B2

公开(公告)日：2013-12-17

申请号：US13070819

申请日：2011-03-24

Applicant: Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L27/088

CPC classification number: H01L29/66477 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.

公开(公告)号：US08525261B2

公开(公告)日：2013-09-03

申请号：US12953200

申请日：2010-11-23

Applicant: Shyi-Yuan Wu ,  Wing Chor Chan ,  Chien-Wen Chu

Inventor： Shyi-Yuan Wu ,  Wing Chor Chan ,  Chien-Wen Chu

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376

Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.

Abstract translation: 半导体器件包括源极区域，漏极区域和源极区域与漏极区域之间的漂移区域。 分离栅极设置在漂移区域的一部分上，并且在源极和漏极区域之间。 分离栅极包括由栅极氧化物层隔开的第一和第二栅电极。 超级结结构设置在栅极和漏极区域之间的漂移区域内。

公开(公告)号：US08525243B2

公开(公告)日：2013-09-03

申请号：US13180236

申请日：2011-07-11

Applicant: Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

Inventor： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC: H01L27/105

CPC classification number: H01L29/6659 ,  H01L27/11558 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/788

Abstract: A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.

Abstract translation: 半导体器件在栅极的两侧具有栅极多个掺杂区域。 栅极可以由晶体管和电容器共享。

公开(公告)号：US08487360B2

公开(公告)日：2013-07-16

申请号：US12876711

申请日：2010-09-07

Applicant: Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu ,  Chin-Pen Yeh

Inventor： Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu ,  Chin-Pen Yeh

IPC: H01L27/112

CPC classification number: H01L27/0629 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.

Abstract translation: 半导体存储器件包括：第一杂质型衬底，衬底中第二杂质类型的第一阱区，第二杂质型不同于第一杂质型;衬底中第一杂质型第二阱区; 在衬底上的图案化的第一介电层延伸在第一和第二阱区上，图案化的第一介电层上的图案化的第一栅极结构，图案化的第一栅极结构上的图案化的第二介电层，以及图案化的第二栅极结构 图案化的第二介电层。 图案化的第一栅极结构可以包括沿第一方向延伸的第一部分和沿与第一部分正交的第二方向延伸的第二部分，其中第一部分和第二部分以交叉图案彼此相交。 图案化的第二栅极结构可以包括在图案化的第一栅极结构的第一部分上的第一方向上延伸的第一部分或者在图案化的第一栅极结构的第二部分上沿第二方向延伸的第二部分中的至少一个。

公开(公告)号：US20130049067A1

公开(公告)日：2013-02-28

申请号：US13222187

申请日：2011-08-31

Applicant: Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

Inventor： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC: H01L27/07 ,  H01L21/331

CPC classification number: H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract translation: 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US08125031B2

公开(公告)日：2012-02-28

申请号：US13100449

申请日：2011-05-04

Applicant: Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

Inventor： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC: H01L29/02

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

公开(公告)号：US20090256183A1

公开(公告)日：2009-10-15

申请号：US12102608

申请日：2008-04-14

Applicant: Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

Inventor： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC: H01L27/105 ,  H01L21/8239

CPC classification number: H01L29/6659 ,  H01L27/11558 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/788

Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.